This is a Verilog project to initialize the ds1302 clock chip and read the time data from the chip. The result of the chip will be shown on an 8 bit LED Common anode digital tube.The picture of running is in picture.doc.

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
.qsys_edit		.qsys_edit
db		db
incremental_db		incremental_db
output_files		output_files
simulation/modelsim		simulation/modelsim
.gitattributes		.gitattributes
README.md		README.md
clkdiv.bsf		clkdiv.bsf
clkdiv.v		clkdiv.v
clkdiv.v.bak		clkdiv.v.bak
cr_ie_info.json		cr_ie_info.json
decoder.bsf		decoder.bsf
decoder.v		decoder.v
decoder.v.bak		decoder.v.bak
ds1302.qpf		ds1302.qpf
ds1302.qsf		ds1302.qsf
ds1302.qws		ds1302.qws
ds1302_nativelink_simulation.rpt		ds1302_nativelink_simulation.rpt
led_seg.bsf		led_seg.bsf
picture.docx		picture.docx
seg_change.v		seg_change.v
seg_change.v.bak		seg_change.v.bak
spi.bsf		spi.bsf
spi.v		spi.v
spi.v.bak		spi.v.bak
stp1.stp		stp1.stp
test.bsf		test.bsf
test.v		test.v
test.v.bak		test.v.bak
test2.v		test2.v
top_level.bdf		top_level.bdf

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