Still Not Fixed

Cherrytree56567 · Oct 21, 2023 · 83304c2 · 83304c2
1 parent 596afd9
commit 83304c2
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Showing 14 changed files with 53 additions and 45 deletions.
diff --git a/PSEMU/Bus.h b/PSEMU/Bus.h
@@ -12,7 +12,6 @@ class Bus {
 
     // Memory Ranges
     const Range BIOS = Range(0x1fc00000, 512 * 1024);
-    const Range SYS_CONTROL = Range(0x1f801000, 36);
     const Range RAM_SIZE = Range(0x1f801060, 4);
     const Range CACHE_CONTROL = Range(0xfffe0130, 4);
     const Range RAM_ = Range(0x00000000, 2 * 1024 * 1024);

diff --git a/PSEMU/CPU.cpp b/PSEMU/CPU.cpp
@@ -641,7 +641,7 @@ void CPU::op_sh(Instruction instruction) {
         uint32_t v    = regs[t];
 
         if (addr % 2 == 0) {
-            bus->store16(addr, (uint16_t)v);
+            store16(addr, (uint16_t)v);
         }
         else {
             exception(Exception::StoreAddressError);
@@ -676,7 +676,7 @@ void CPU::op_sb(Instruction instruction) {
     uint32_t addr = regs[s] + i;
     uint32_t v = regs[t];
 
-    bus->store8(addr, (uint8_t)v);
+    store8(addr, (uint8_t)v);
 }
 
 void CPU::op_jr(Instruction instruction) {
@@ -699,7 +699,7 @@ void CPU::op_lb(Instruction instruction) {
     uint8_t v = bus->load8(addr);
 
     // Put the load in the delay slot
-    load = std::make_tuple(t, v);
+    load = std::make_tuple(t, (uint8_t)v);
 }
 
 void CPU::op_beq(Instruction instruction) {
@@ -761,7 +761,7 @@ void CPU::op_bgtz(Instruction instruction) {
     uint32_t i = instruction.imm_s();
     uint32_t s = instruction.rs();
 
-    uint32_t v = regs[s];
+    int32_t v = regs[s];
 
     if (v > 0) {
         branch(i);
@@ -772,7 +772,7 @@ void CPU::op_blez(Instruction instruction) {
     uint32_t i = instruction.imm_s();
     uint32_t s = instruction.rs();
 
-    uint32_t v = regs[s];
+    int32_t v = regs[s];
 
     if (v <= 0) {
         branch(i);
@@ -814,7 +814,7 @@ void CPU::op_bxx(Instruction instruction) {
     uint32_t is_bgez = (instructiona >> 16) & 1;
     uint32_t is_link = (instructiona >> 20) & 1 != 0;
 
-    uint32_t v = regs[s];
+    int32_t v = regs[s];
 
     // Test "less than zero"
     uint32_t test = (v < 0);
@@ -840,7 +840,7 @@ void CPU::op_slti(Instruction instruction) {
     uint32_t s = instruction.rs();
     uint32_t t = instruction.rt();
 
-    uint32_t v = (regs[s]) < i;
+    uint32_t v = ((int32_t)regs[s]) < i;
 
     set_reg(t, v);
 }
@@ -860,7 +860,7 @@ void CPU::op_sra(Instruction instruction) {
     uint32_t t = instruction.rt();
     uint32_t d = instruction.rd();
 
-    uint32_t v = ((uint32_t)regs[t]) >> i;
+    uint32_t v = ((int32_t)regs[t]) >> i;
 
     set_reg(d, v);
 }
@@ -945,12 +945,12 @@ void CPU::op_slt(Instruction instruction) {
     uint32_t s = instruction.rs();
     uint32_t t = instruction.rt();
 
-    s = regs[s];
-    t = regs[t];
+    int32_t sa = regs[s];
+    int32_t ta = regs[t];
 
-    uint32_t v = s < t;
+    int32_t v = s < t;
 
-    set_reg(d, v);
+    set_reg(d, (uint32_t)v);
 }
 
 void CPU::exception(Exception causea) {
@@ -1018,7 +1018,7 @@ void CPU::op_lhu(Instruction instruction) {
         uint16_t v = bus->load16(addr);
 
         // Put the load in the delay slot
-        load = std::make_tuple(t, v);
+        load = std::make_tuple(t, (uint32_t)v);
     } else {
         exception(Exception::LoadAddressError);
     }
@@ -1046,15 +1046,15 @@ void CPU::op_lh(Instruction instruction) {
     uint16_t v = bus->load16(addr);
 
     // Put the load in the delay slot
-    load = std::make_tuple(t, v);
+    load = std::make_tuple(t, (uint32_t)v);
 }
 
 void CPU::op_nor(Instruction instruction) {
     uint32_t d = instruction.rd();
     uint32_t s = instruction.rs();
     uint32_t t = instruction.rt();
 
-    uint32_t v = !(regs[s] | regs[t]);
+    uint32_t v = ~(regs[s] | regs[t]);
 
     set_reg(d, v);
 }
@@ -1065,7 +1065,7 @@ void CPU::op_srav(Instruction instruction) {
     uint32_t t = instruction.rt();
 
     // Shift amount is truncated to 5 bits
-    uint32_t v = (regs[t] >> (regs[s] & 0x1f));
+    uint32_t v = ((int32_t)regs[t]) >> (regs[s] & 0x1f);
 
     set_reg(d, v);
 }
@@ -1082,10 +1082,16 @@ void CPU::op_srlv(Instruction instruction) {
 }
 
 void CPU::op_multu(Instruction instruction) {
-    uint64_t value = (uint64_t)regs[instruction.rs()] * (uint64_t)regs[instruction.rt()];
+    uint32_t s = instruction.rs();
+    uint32_t t = instruction.rt();
+
+    uint64_t a = regs[s];
+    uint64_t b = regs[t];
 
-    hi = (uint32_t)(value >> 32);
-    lo = (uint32_t)value;
+    uint32_t v = a * b;
+
+    hi = (uint32_t)(v >> 32);
+    lo = (uint32_t)v;
 }
 
 void CPU::op_xor(Instruction instruction) {
@@ -1103,10 +1109,16 @@ void CPU::op_break(Instruction instruction) {
 }
 
 void CPU::op_mult(Instruction instruction) {
-    int64_t value = (int64_t)(int)regs[instruction.rs()] * (int64_t)(int)regs[instruction.rt()]; //sign extend to pass amidog cpu test
+    uint32_t s = instruction.rs();
+    uint32_t t = instruction.rt();
+
+    uint64_t a = ((uint32_t)regs[s]);
+    uint64_t b = ((uint32_t)regs[t]);
+
+    uint64_t v = (a * b);
 
-    hi = (uint32_t)(value >> 32);
-    lo = (uint32_t)value;
+    hi = (uint32_t)(v >> 32);
+    lo = (uint32_t)v;
 }
 
 void CPU::op_sub(Instruction instruction) {
@@ -1148,7 +1160,7 @@ void CPU::op_lwl(Instruction instruction) {
     uint32_t t = instruction.rt();
     uint32_t s = instruction.rs();
 
-    uint32_t addr = regs[s] + static_cast<int32_t>(i);
+    uint32_t addr = regs[s] + i;
 
     // This instruction bypasses the load delay restriction: this
     // instruction will merge the new contents with the value
@@ -1165,16 +1177,16 @@ void CPU::op_lwl(Instruction instruction) {
     uint32_t v;
     switch (addr & 3U) {
     case 0:
-        v = (cur_v & 0x00FFFFFFU) | (aligned_word << 24);
+        v = (cur_v & 0x00FFFFFF) | (aligned_word << 24);
         break;
     case 1:
-        v = (cur_v & 0x0000FFFFU) | (aligned_word << 16);
+        v = (cur_v & 0x0000FFFF) | (aligned_word << 16);
         break;
     case 2:
-        v = (cur_v & 0x000000FFU) | (aligned_word << 8);
+        v = (cur_v & 0x000000FF) | (aligned_word << 8);
         break;
     case 3:
-        v = (cur_v & 0x00000000U) | (aligned_word);
+        v = (cur_v & 0x00000000) | (aligned_word);
         break;
     default:
         throw std::runtime_error("Unreachable code");
@@ -1236,24 +1248,24 @@ void CPU::op_swl(Instruction instruction) {
     uint32_t addr = regs[s] + i;
     uint32_t v = regs[t];
 
-    uint32_t aligned_addr = addr & ~3U;
+    uint32_t aligned_addr = addr & ~3;
 
     // Load the current value for the aligned word at the target address
     uint32_t cur_mem = bus->load32(aligned_addr);
 
     uint32_t mem;
     switch (addr & 3U) {
     case 0:
-        mem = (cur_mem & 0xFFFFFF00U) | (v >> 24);
+        mem = (cur_mem & 0xFFFFFF00) | (v >> 24);
         break;
     case 1:
-        mem = (cur_mem & 0xFFFF0000U) | (v >> 16);
+        mem = (cur_mem & 0xFFFF0000) | (v >> 16);
         break;
     case 2:
-        mem = (cur_mem & 0xFF000000U) | (v >> 8);
+        mem = (cur_mem & 0xFF000000) | (v >> 8);
         break;
     case 3:
-        mem = (cur_mem & 0x00000000U) | (v);
+        mem = (cur_mem & 0x00000000) | (v >> 0);
         break;
     default:
         throw std::runtime_error("Unreachable code");
@@ -1263,31 +1275,31 @@ void CPU::op_swl(Instruction instruction) {
 }
 
 void CPU::op_swr(Instruction instruction) {
-    int32_t i = instruction.imm_s();
+    uint32_t i = instruction.imm_s();
     uint32_t t = instruction.rt();
     uint32_t s = instruction.rs();
 
     uint32_t addr = regs[s] + i;
     uint32_t v = regs[t];
 
-    uint32_t aligned_addr = addr & ~3U;
+    uint32_t aligned_addr = addr & ~3;
 
     // Load the current value for the aligned word at the target address
     uint32_t cur_mem = bus->load32(aligned_addr);
 
     uint32_t mem;
     switch (addr & 3U) {
     case 0:
-        mem = (cur_mem & 0x00000000U) | (v);
+        mem = (cur_mem & 0x00000000) | (v << 0);
         break;
     case 1:
-        mem = (cur_mem & 0x000000FFU) | (v << 8);
+        mem = (cur_mem & 0x000000FF) | (v << 8);
         break;
     case 2:
-        mem = (cur_mem & 0x0000FFFFU) | (v << 16);
+        mem = (cur_mem & 0x0000FFFF) | (v << 16);
         break;
     case 3:
-        mem = (cur_mem & 0x00FFFFFFU) | (v << 24);
+        mem = (cur_mem & 0x00FFFFFF) | (v << 24);
         break;
     default:
         throw std::runtime_error("Unreachable code");

diff --git a/PSEMU/RAM.cpp b/PSEMU/RAM.cpp
@@ -2,7 +2,7 @@
 
 void RAM::newl() {
 	for (int i = 0; i < (2 * 1024 * 1024); i++) {
-		ram[i] = 0x0;
+		ram[i] = 0xca;
 	}
 }
 

diff --git a/PSEMU/x64/Debug/CPU.obj b/PSEMU/x64/Debug/CPU.obj
diff --git a/PSEMU/x64/Debug/PSEMU.ilk b/PSEMU/x64/Debug/PSEMU.ilk
diff --git a/PSEMU/x64/Debug/PSEMU.log b/PSEMU/x64/Debug/PSEMU.log
@@ -3,9 +3,6 @@ C:\Users\ronit\Desktop\PSEMU\PSEMU\CPU.h(114,1): warning C4554: '&': check opera
 C:\Users\ronit\Desktop\PSEMU\PSEMU\CPU.h(123,1): warning C4554: '&': check operator precedence for possible error; use parentheses to clarify precedence
 C:\Users\ronit\Desktop\PSEMU\PSEMU\CPU.h(132,1): warning C4554: '&': check operator precedence for possible error; use parentheses to clarify precedence
 C:\Users\ronit\Desktop\PSEMU\PSEMU\CPU.cpp(815,53): warning C4554: '&': check operator precedence for possible error; use parentheses to clarify precedence
-  PSEMU.cpp
-C:\Users\ronit\Desktop\PSEMU\PSEMU\CPU.h(114,1): warning C4554: '&': check operator precedence for possible error; use parentheses to clarify precedence
-C:\Users\ronit\Desktop\PSEMU\PSEMU\CPU.h(123,1): warning C4554: '&': check operator precedence for possible error; use parentheses to clarify precedence
-C:\Users\ronit\Desktop\PSEMU\PSEMU\CPU.h(132,1): warning C4554: '&': check operator precedence for possible error; use parentheses to clarify precedence
-  Generating Code...
+C:\Users\ronit\Desktop\PSEMU\PSEMU\CPU.cpp(1091,16): warning C4244: 'initializing': conversion from 'uint64_t' to 'uint32_t', possible loss of data
+C:\Users\ronit\Desktop\PSEMU\PSEMU\CPU.cpp(1093,23): warning C4293: '>>': shift count negative or too big, undefined behavior
   PSEMU.vcxproj -> C:\Users\ronit\Desktop\PSEMU\x64\Debug\PSEMU.exe
diff --git a/PSEMU/x64/Debug/PSEMU.tlog/CL.command.1.tlog b/PSEMU/x64/Debug/PSEMU.tlog/CL.command.1.tlog
diff --git a/PSEMU/x64/Debug/PSEMU.tlog/CL.read.1.tlog b/PSEMU/x64/Debug/PSEMU.tlog/CL.read.1.tlog
diff --git a/PSEMU/x64/Debug/PSEMU.tlog/CL.write.1.tlog b/PSEMU/x64/Debug/PSEMU.tlog/CL.write.1.tlog
diff --git a/PSEMU/x64/Debug/PSEMU.tlog/link.read.1.tlog b/PSEMU/x64/Debug/PSEMU.tlog/link.read.1.tlog
diff --git a/PSEMU/x64/Debug/vc143.idb b/PSEMU/x64/Debug/vc143.idb
diff --git a/PSEMU/x64/Debug/vc143.pdb b/PSEMU/x64/Debug/vc143.pdb
diff --git a/x64/Debug/PSEMU.exe b/x64/Debug/PSEMU.exe
diff --git a/x64/Debug/PSEMU.pdb b/x64/Debug/PSEMU.pdb