Skip to content

Commit

Permalink
Update OTG LLD close to AT32 instead STM32 and patch some issues
Browse files Browse the repository at this point in the history
  • Loading branch information
@HorrorTroll
HorrorTroll committed Feb 29, 2024
1 parent 02b0d87 commit 2e613d0
Show file tree
Hide file tree
Showing 9 changed files with 428 additions and 478 deletions.
2 changes: 1 addition & 1 deletion os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -204,4 +204,4 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
* @}
*/

/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/
/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/
11 changes: 3 additions & 8 deletions os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -470,10 +470,7 @@ typedef struct
{
__IO uint32_t EVTOUT; /*!< IOMUX Event output control register, Address offset: 0x00 */
__IO uint32_t REMAP; /*!< IOMUX remap register 1, Address offset: 0x04 */
__IO uint32_t EXINTC1; /*!< IOMUX external interrupt config register 1, Address offset: 0x08 */
__IO uint32_t EXINTC2; /*!< IOMUX external interrupt config register 2, Address offset: 0x0C */
__IO uint32_t EXINTC3; /*!< IOMUX external interrupt config register 3, Address offset: 0x10 */
__IO uint32_t EXINTC4; /*!< IOMUX external interrupt config register 4, Address offset: 0x14 */
__IO uint32_t EXINTC[4]; /*!< IOMUX external interrupt config register, Address offset: 0x08 ~ 0x14 */
uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
__IO uint32_t REMAP2; /*!< IOMUX remap register 2, Address offset: 0x1C */
__IO uint32_t REMAP3; /*!< IOMUX remap register 3, Address offset: 0x20 */
Expand Down Expand Up @@ -696,9 +693,7 @@ typedef struct

#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */
#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
#define UID1_BASE 0x1FFFF7E8U /*!< Unique device ID register 1 base address */
#define UID2_BASE 0x1FFFF7ECU /*!< Unique device ID register 2 base address */
#define UID3_BASE 0x1FFFF7F0U /*!< Unique device ID register 3 base address */
#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
#define USD_BASE 0x1FFFF800U /*!< FLASH User System Data base address */

#define DEBUG_BASE 0xE0042000U /*!< Debug MCU registers base address */
Expand Down Expand Up @@ -10494,4 +10489,4 @@ typedef struct

#endif /* __AT32F415Cx_H */

/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/
/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/
11 changes: 3 additions & 8 deletions os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -469,10 +469,7 @@ typedef struct
{
__IO uint32_t EVTOUT; /*!< IOMUX Event output control register, Address offset: 0x00 */
__IO uint32_t REMAP; /*!< IOMUX remap register 1, Address offset: 0x04 */
__IO uint32_t EXINTC1; /*!< IOMUX external interrupt config register 1, Address offset: 0x08 */
__IO uint32_t EXINTC2; /*!< IOMUX external interrupt config register 2, Address offset: 0x0C */
__IO uint32_t EXINTC3; /*!< IOMUX external interrupt config register 3, Address offset: 0x10 */
__IO uint32_t EXINTC4; /*!< IOMUX external interrupt config register 4, Address offset: 0x14 */
__IO uint32_t EXINTC[4]; /*!< IOMUX external interrupt config register, Address offset: 0x08 ~ 0x14 */
uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
__IO uint32_t REMAP2; /*!< IOMUX remap register 2, Address offset: 0x1C */
__IO uint32_t REMAP3; /*!< IOMUX remap register 3, Address offset: 0x20 */
Expand Down Expand Up @@ -694,9 +691,7 @@ typedef struct

#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */
#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
#define UID1_BASE 0x1FFFF7E8U /*!< Unique device ID register 1 base address */
#define UID2_BASE 0x1FFFF7ECU /*!< Unique device ID register 2 base address */
#define UID3_BASE 0x1FFFF7F0U /*!< Unique device ID register 3 base address */
#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
#define USD_BASE 0x1FFFF800U /*!< FLASH User System Data base address */

#define DEBUG_BASE 0xE0042000U /*!< Debug MCU registers base address */
Expand Down Expand Up @@ -10444,4 +10439,4 @@ typedef struct

#endif /* __AT32F415Kx_H */

/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/
/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/
11 changes: 3 additions & 8 deletions os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -472,10 +472,7 @@ typedef struct
{
__IO uint32_t EVTOUT; /*!< IOMUX Event output control register, Address offset: 0x00 */
__IO uint32_t REMAP; /*!< IOMUX remap register 1, Address offset: 0x04 */
__IO uint32_t EXINTC1; /*!< IOMUX external interrupt config register 1, Address offset: 0x08 */
__IO uint32_t EXINTC2; /*!< IOMUX external interrupt config register 2, Address offset: 0x0C */
__IO uint32_t EXINTC3; /*!< IOMUX external interrupt config register 3, Address offset: 0x10 */
__IO uint32_t EXINTC4; /*!< IOMUX external interrupt config register 4, Address offset: 0x14 */
__IO uint32_t EXINTC[4]; /*!< IOMUX external interrupt config register, Address offset: 0x08 ~ 0x14 */
uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
__IO uint32_t REMAP2; /*!< IOMUX remap register 2, Address offset: 0x1C */
__IO uint32_t REMAP3; /*!< IOMUX remap register 3, Address offset: 0x20 */
Expand Down Expand Up @@ -700,9 +697,7 @@ typedef struct

#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */
#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
#define UID1_BASE 0x1FFFF7E8U /*!< Unique device ID register 1 base address */
#define UID2_BASE 0x1FFFF7ECU /*!< Unique device ID register 2 base address */
#define UID3_BASE 0x1FFFF7F0U /*!< Unique device ID register 3 base address */
#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
#define USD_BASE 0x1FFFF800U /*!< FLASH User System Data base address */

#define DEBUG_BASE 0xE0042000U /*!< Debug MCU registers base address */
Expand Down Expand Up @@ -10537,4 +10532,4 @@ typedef struct

#endif /* __AT32F415Rx_H */

/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/
/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/
2 changes: 1 addition & 1 deletion os/common/ext/CMSIS/ArteryTek/AT32F415/system_at32f415.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -109,4 +109,4 @@ extern void SystemCoreClockUpdate(void);
* @}
*/

/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/
/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/
2 changes: 1 addition & 1 deletion os/hal/ports/AT32/LLD/EXINTv1/at32_exint1.inc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -82,7 +82,7 @@ OSAL_IRQ_HANDLER(AT32_EXINT1_HANDLER) {

OSAL_IRQ_PROLOGUE();

extiGetAndClearGroup1(1U << 1, intsts);
exintGetAndClearGroup1(1U << 1, intsts);

exint_serve_irq(intsts, 1);

Expand Down
Loading

0 comments on commit 2e613d0

Please sign in to comment.