HT32: SPI: avoid write collisions when SPI FIFO is disabled #361
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This fixes possible write collisions experienced when SPI FIFO is disabled due to not checking whether the SPI shift register is empty before writing. This is done by checking TXE flag instead of TXBE flag when the FIFO is not used.
fpoussin
approved these changes
Jul 17, 2023
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This improves SPI transmission reliability when SPI FIFO is not used. Without this change, I experienced hangups when frequently transmitting data to SPI flash.
For reference:
When SPI FIFO is enabled, a write collision occurs when writing to SPIDR register while both the TX buffer and SPI shift register are full (which is when TXE flag is not asserted).
When SPI FIFO is disabled, a write collision occurs when writing to SPIDR register while both TX FIFO and TX shift register are full. Here, the TXBE flag remains appropriate since it is used to check when TX buffer is empty and when the TX FIFO is below a set threshold value.