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Patch update for AT32F415 #395

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merged 3 commits into from
Apr 3, 2024
Merged

Patch update for AT32F415 #395

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2e613d0
Update OTG LLD close to AT32 instead STM32 and patch some issues
HorrorTroll Feb 29, 2024
91f6283
Update registry for DMAMUX channel
HorrorTroll Mar 2, 2024
b8b233a
Small changes
HorrorTroll Mar 30, 2024
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2 changes: 1 addition & 1 deletion os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415.h
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Expand Up @@ -204,4 +204,4 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
* @}
*/

/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/
/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/
11 changes: 3 additions & 8 deletions os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h
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Expand Up @@ -470,10 +470,7 @@ typedef struct
{
__IO uint32_t EVTOUT; /*!< IOMUX Event output control register, Address offset: 0x00 */
__IO uint32_t REMAP; /*!< IOMUX remap register 1, Address offset: 0x04 */
__IO uint32_t EXINTC1; /*!< IOMUX external interrupt config register 1, Address offset: 0x08 */
__IO uint32_t EXINTC2; /*!< IOMUX external interrupt config register 2, Address offset: 0x0C */
__IO uint32_t EXINTC3; /*!< IOMUX external interrupt config register 3, Address offset: 0x10 */
__IO uint32_t EXINTC4; /*!< IOMUX external interrupt config register 4, Address offset: 0x14 */
__IO uint32_t EXINTC[4]; /*!< IOMUX external interrupt config register, Address offset: 0x08 ~ 0x14 */
uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
__IO uint32_t REMAP2; /*!< IOMUX remap register 2, Address offset: 0x1C */
__IO uint32_t REMAP3; /*!< IOMUX remap register 3, Address offset: 0x20 */
Expand Down Expand Up @@ -696,9 +693,7 @@ typedef struct

#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */
#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
#define UID1_BASE 0x1FFFF7E8U /*!< Unique device ID register 1 base address */
#define UID2_BASE 0x1FFFF7ECU /*!< Unique device ID register 2 base address */
#define UID3_BASE 0x1FFFF7F0U /*!< Unique device ID register 3 base address */
#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
#define USD_BASE 0x1FFFF800U /*!< FLASH User System Data base address */

#define DEBUG_BASE 0xE0042000U /*!< Debug MCU registers base address */
Expand Down Expand Up @@ -10494,4 +10489,4 @@ typedef struct

#endif /* __AT32F415Cx_H */

/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/
/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/
11 changes: 3 additions & 8 deletions os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h
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Expand Up @@ -469,10 +469,7 @@ typedef struct
{
__IO uint32_t EVTOUT; /*!< IOMUX Event output control register, Address offset: 0x00 */
__IO uint32_t REMAP; /*!< IOMUX remap register 1, Address offset: 0x04 */
__IO uint32_t EXINTC1; /*!< IOMUX external interrupt config register 1, Address offset: 0x08 */
__IO uint32_t EXINTC2; /*!< IOMUX external interrupt config register 2, Address offset: 0x0C */
__IO uint32_t EXINTC3; /*!< IOMUX external interrupt config register 3, Address offset: 0x10 */
__IO uint32_t EXINTC4; /*!< IOMUX external interrupt config register 4, Address offset: 0x14 */
__IO uint32_t EXINTC[4]; /*!< IOMUX external interrupt config register, Address offset: 0x08 ~ 0x14 */
uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
__IO uint32_t REMAP2; /*!< IOMUX remap register 2, Address offset: 0x1C */
__IO uint32_t REMAP3; /*!< IOMUX remap register 3, Address offset: 0x20 */
Expand Down Expand Up @@ -694,9 +691,7 @@ typedef struct

#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */
#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
#define UID1_BASE 0x1FFFF7E8U /*!< Unique device ID register 1 base address */
#define UID2_BASE 0x1FFFF7ECU /*!< Unique device ID register 2 base address */
#define UID3_BASE 0x1FFFF7F0U /*!< Unique device ID register 3 base address */
#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
#define USD_BASE 0x1FFFF800U /*!< FLASH User System Data base address */

#define DEBUG_BASE 0xE0042000U /*!< Debug MCU registers base address */
Expand Down Expand Up @@ -10444,4 +10439,4 @@ typedef struct

#endif /* __AT32F415Kx_H */

/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/
/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/
11 changes: 3 additions & 8 deletions os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h
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Expand Up @@ -472,10 +472,7 @@ typedef struct
{
__IO uint32_t EVTOUT; /*!< IOMUX Event output control register, Address offset: 0x00 */
__IO uint32_t REMAP; /*!< IOMUX remap register 1, Address offset: 0x04 */
__IO uint32_t EXINTC1; /*!< IOMUX external interrupt config register 1, Address offset: 0x08 */
__IO uint32_t EXINTC2; /*!< IOMUX external interrupt config register 2, Address offset: 0x0C */
__IO uint32_t EXINTC3; /*!< IOMUX external interrupt config register 3, Address offset: 0x10 */
__IO uint32_t EXINTC4; /*!< IOMUX external interrupt config register 4, Address offset: 0x14 */
__IO uint32_t EXINTC[4]; /*!< IOMUX external interrupt config register, Address offset: 0x08 ~ 0x14 */
uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
__IO uint32_t REMAP2; /*!< IOMUX remap register 2, Address offset: 0x1C */
__IO uint32_t REMAP3; /*!< IOMUX remap register 3, Address offset: 0x20 */
Expand Down Expand Up @@ -700,9 +697,7 @@ typedef struct

#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */
#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
#define UID1_BASE 0x1FFFF7E8U /*!< Unique device ID register 1 base address */
#define UID2_BASE 0x1FFFF7ECU /*!< Unique device ID register 2 base address */
#define UID3_BASE 0x1FFFF7F0U /*!< Unique device ID register 3 base address */
#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
#define USD_BASE 0x1FFFF800U /*!< FLASH User System Data base address */

#define DEBUG_BASE 0xE0042000U /*!< Debug MCU registers base address */
Expand Down Expand Up @@ -10537,4 +10532,4 @@ typedef struct

#endif /* __AT32F415Rx_H */

/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/
/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/
2 changes: 1 addition & 1 deletion os/common/ext/CMSIS/ArteryTek/AT32F415/system_at32f415.h
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Expand Up @@ -109,4 +109,4 @@ extern void SystemCoreClockUpdate(void);
* @}
*/

/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/
/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/
4 changes: 1 addition & 3 deletions os/hal/boards/AT_START_F415/board.h
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Expand Up @@ -173,7 +173,6 @@
* PA0 - Normal input (GPIOA_BUTTON)
* PA2 - Alternate output (GPIOA_ARD_D1, GPIOA_USART2_TX)
* PA3 - Normal input (GPIOA_ARD_D0, GPIOA_USART2_RX)
* PA13 - Pull-up input (GPIOA_SWDIO)
* PA14 - Pull-down input (GPIOA_SWCLK)
*/
#define VAL_GPIOACFGLR 0x88884B84 /* PA7...PA0 */
Expand All @@ -182,8 +181,6 @@

/*
* Port B setup.
* Everything input with pull-up except:
* PB3 - Pull-up input (GPIOB_SWO)
*/
#define VAL_GPIOBCFGLR 0x88888888 /* PB7...PB0 */
#define VAL_GPIOBCFGHR 0x88888888 /* PB15...PB8 */
Expand All @@ -203,6 +200,7 @@

/*
* Port D setup.
* Everything input with pull-up except:
* PD0 - Normal input (GPIOD_OSC_IN).
* PD1 - Normal input (GPIOD_OSC_OUT).
*/
Expand Down
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