frequency divider circuit that outputs three different clocks with(50 Khz, 100 Khz and 250 Khz).
- Clock 1 : 250 Khz
- Clock 2 : 100 Khz
- Clock 3 : 50 Khz
the verilog code was tested in ModelSim using ModelSim simulator, you can check the simulation by reviewing the @simulation