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Merge pull request #3 from binary1230/sync-w-upstream-5-26-21
Sync w upstream devinacker
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@@ -11,3 +11,4 @@ | |
| *.rar | ||
| */out | ||
| */bin | ||
| .idea | ||
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| ; default registers used for Super Game Boy | ||
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| [labels] | ||
| 00:FF00 GB.JOYP | ||
| 00:FF01 GB.SB | ||
| 00:FF02 GB.SC | ||
| 00:FF04 GB.DIV | ||
| 00:FF05 GB.TIMA | ||
| 00:FF06 GB.TMA | ||
| 00:FF07 GB.TAC | ||
| 00:FF0F GB.IF | ||
| 00:FF10 GB.NR10 | ||
| 00:FF11 GB.NR11 | ||
| 00:FF12 GB.NR12 | ||
| 00:FF13 GB.NR13 | ||
| 00:FF14 GB.NR14 | ||
| 00:FF16 GB.NR21 | ||
| 00:FF17 GB.NR22 | ||
| 00:FF18 GB.NR23 | ||
| 00:FF19 GB.NR24 | ||
| 00:FF1A GB.NR30 | ||
| 00:FF1B GB.NR31 | ||
| 00:FF1C GB.NR32 | ||
| 00:FF1D GB.NR33 | ||
| 00:FF1E GB.NR34 | ||
| 00:FF20 GB.NR41 | ||
| 00:FF21 GB.NR42 | ||
| 00:FF22 GB.NR43 | ||
| 00:FF23 GB.NR44 | ||
| 00:FF24 GB.NR50 | ||
| 00:FF25 GB.NR51 | ||
| 00:FF26 GB.NR52 | ||
| 00:FF40 GB.LCDC | ||
| 00:FF41 GB.STAT | ||
| 00:FF42 GB.SCY | ||
| 00:FF43 GB.SCX | ||
| 00:FF44 GB.LY | ||
| 00:FF45 GB.LYC | ||
| 00:FF46 GB.DMA | ||
| 00:FF47 GB.BGP | ||
| 00:FF48 GB.OBP0 | ||
| 00:FF49 GB.OBP1 | ||
| 00:FF4A GB.WY | ||
| 00:FF4B GB.WX | ||
| 00:FFFF GB.IE |
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| Original file line number | Diff line number | Diff line change |
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| #ifdef SUPERGAMEBOY_CPP | ||
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| uint16 SGBDebugger::relb(int8 offset, int op_len, uint16 pc) { | ||
| return pc + op_len + offset; | ||
| } | ||
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| uint8 SGBDebugger::dreadb(uint16 addr) { | ||
| SNES::debugger.bus_access = true; | ||
| return supergameboy.read_gb(addr); | ||
| SNES::debugger.bus_access = false; | ||
| } | ||
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| uint16 SGBDebugger::dreadw(uint16 addr) { | ||
| uint16 r; | ||
| r = dreadb(addr + 0) << 0; | ||
| r |= dreadb(addr + 1) << 8; | ||
| return r; | ||
| } | ||
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| uint24 SGBDebugger::decode(uint8 offset_type, uint16 addr, uint16 pc) { | ||
| uint24 r = 0; | ||
| uint16 dp = 0xff00; | ||
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| switch(offset_type) { | ||
| case GBCPU::Addr8Ptr: | ||
| r = dp | (uint8)addr; | ||
| break; | ||
| case GBCPU::Addr16: | ||
| case GBCPU::Addr16Ptr: | ||
| r = addr; | ||
| break; | ||
| case GBCPU::RegBCPtr: | ||
| r = getRegister(RegisterBC); | ||
| break; | ||
| case GBCPU::RegCPtr: | ||
| r = dp | (uint8)getRegister(RegisterBC); | ||
| break; | ||
| case GBCPU::RegDEPtr: | ||
| r = getRegister(RegisterDE); | ||
| break; | ||
| case GBCPU::RegHLPtr: | ||
| case GBCPU::RegHLPtrInc: | ||
| case GBCPU::RegHLPtrDec: | ||
| case GBCPU::PrefixCB: | ||
| r = getRegister(RegisterHL); | ||
| break; | ||
| case GBCPU::PCRelative: | ||
| r = relb((int8)addr, 2, pc); | ||
| break; | ||
| case GBCPU::SPRelative: | ||
| r = relb((int8)addr, 2, getRegister(RegisterSP)); | ||
| break; | ||
| case GBCPU::RST: | ||
| r = dreadb(pc) & 0x38; | ||
| break; | ||
| } | ||
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| if (r > 0x4000 && sgb_addr_with_bank) { | ||
| r = sgb_addr_with_bank(r); | ||
| } | ||
| return r; | ||
| } | ||
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| void SGBDebugger::disassemble_opcode_ex(SGBDebugger::Opcode &opcode, uint24 addr) { | ||
| uint8 param[3]; | ||
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| SNES::debugger.bus_access = true; | ||
| param[0] = read_gb(addr + 0); | ||
| param[1] = read_gb(addr + 1); | ||
| param[2] = read_gb(addr + 2); | ||
| SNES::debugger.bus_access = false; | ||
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| const GBCPU::OpcodeInfo& op = gbOpcodeInfo[param[0]]; | ||
| opcode.set(0, op.mode0, op.mode1, op.name, param, GBCPU::getOpcodeLength(param[0]) - 1); | ||
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| switch (param[0]) { | ||
| case 0x18: case 0xc3: case 0xe9: | ||
| opcode.flags |= Opcode::FLAG_BRA; break; | ||
| case 0x20: case 0x28: case 0x30: case 0x38: | ||
| case 0xc2: case 0xc4: case 0xc7: case 0xcc: | ||
| case 0xcd: case 0xcf: case 0xd4: case 0xd7: | ||
| case 0xdc: case 0xdf: case 0xe7: case 0xef: | ||
| case 0xf7: case 0xff: | ||
| opcode.flags |= Opcode::FLAG_BRA_CONTINUE; break; | ||
| case 0xc9: case 0xd9: | ||
| opcode.flags |= Opcode::FLAG_RETURN; break; | ||
| case 0xf1: | ||
| opcode.flags |= Opcode::FLAG_POP_F; break; | ||
| case 0xf5: | ||
| opcode.flags |= Opcode::FLAG_PUSH_F; break; | ||
| } | ||
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| if (GBCPU::getOpcodeIndirect(param[0], param[1])) { | ||
| opcode.flags |= Opcode::FLAG_INDIRECT; | ||
| } | ||
| } | ||
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| void SGBDebugger::disassemble_opcode(char *output, uint24 addr) { | ||
| char t[256]; | ||
| char *s = output; | ||
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| sprintf(s, "%.6x ", addr); | ||
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| uint8 op = read_gb(addr); | ||
| uint8 op0 = read_gb(addr + 1); | ||
| uint8 op1 = read_gb(addr + 2); | ||
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| sprintf(t, "%-23s ", nall::GBCPU::disassemble((uint16)addr, op, op0, op1)()); | ||
| strcat(s, t); | ||
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| uint16_t af = getRegister(RegisterAF); | ||
| uint16_t bc = getRegister(RegisterBC); | ||
| uint16_t de = getRegister(RegisterDE); | ||
| uint16_t hl = getRegister(RegisterHL); | ||
| uint16_t sp = getRegister(RegisterSP); | ||
| sprintf(t, "AF:%.4x BC:%.4x DE:%.4x HL:%.4x SP:%.4x ", af, bc, de, hl, sp); | ||
| strcat(s, t); | ||
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| sprintf(t, "%c%c%c%c ", | ||
| (af & 0x80) ? 'Z' : '.', (af & 0x40) ? 'N' : '.', | ||
| (af & 0x20) ? 'H' : '.', (af & 0x10) ? 'C' : '.'); | ||
| strcat(s, t); | ||
| } | ||
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| #endif |
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