Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Decoder jtag: append to list in constant time #511

Open
wants to merge 1 commit into
base: master
Choose a base branch
from
Open

Decoder jtag: append to list in constant time #511

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Jump to
Jump to file
Failed to load files.
Diff view
Diff view
45 changes: 25 additions & 20 deletions libsigrokdecode4DSL/decoders/jtag/pd.py
100644 → 100755
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -200,18 +200,18 @@ def handle_rising_tck_edge(self, tdi, tdo, tck, tms, trst, srst, rtck):
self.ss_bitstring = self.samplenum

if self.bits_cnt > 1:
self.putx([16, [str(self.bits_tdi[0])]])
self.putx([17, [str(self.bits_tdo[0])]])
self.putx([16, [str(self.bits_tdi[-1])]])
self.putx([17, [str(self.bits_tdo[-1])]])
# Use self.samplenum as ES of the previous bit.
self.bits_samplenums_tdi[0][1] = self.samplenum
self.bits_samplenums_tdo[0][1] = self.samplenum
self.bits_samplenums_tdi[-1][1] = self.samplenum
self.bits_samplenums_tdo[-1][1] = self.samplenum

self.bits_tdi.insert(0, tdi)
self.bits_tdo.insert(0, tdo)
self.bits_tdi.append(tdi)
self.bits_tdo.append(tdo)

# Use self.samplenum as SS of the current bit.
self.bits_samplenums_tdi.insert(0, [self.samplenum, -1])
self.bits_samplenums_tdo.insert(0, [self.samplenum, -1])
self.bits_samplenums_tdi.append([self.samplenum, -1])
self.bits_samplenums_tdo.append([self.samplenum, -1])

self.bits_cnt = self.bits_cnt + 1

Expand All @@ -223,25 +223,25 @@ def handle_rising_tck_edge(self, tdi, tdo, tck, tms, trst, srst, rtck):
if self.bits_cnt > 0:
if self.bits_cnt == 1: # Only shift one bit
self.ss_bitstring = self.samplenum
self.bits_tdi.insert(0, tdi)
self.bits_tdo.insert(0, tdo)
self.bits_tdi.append(tdi)
self.bits_tdo.append(tdo)
## Use self.samplenum as SS of the current bit.
self.bits_samplenums_tdi.insert(0, [self.samplenum, -1])
self.bits_samplenums_tdo.insert(0, [self.samplenum, -1])
self.bits_samplenums_tdi.append([self.samplenum, -1])
self.bits_samplenums_tdo.append([self.samplenum, -1])
else:
### ----------------------------------------------------------------
self.putx([16, [str(self.bits_tdi[0])]])
self.putx([17, [str(self.bits_tdo[0])]])
self.putx([16, [str(self.bits_tdi[-1])]])
self.putx([17, [str(self.bits_tdo[-1])]])
### Use self.samplenum as ES of the previous bit.
self.bits_samplenums_tdi[0][1] = self.samplenum
self.bits_samplenums_tdo[0][1] = self.samplenum
self.bits_samplenums_tdi[-1][1] = self.samplenum
self.bits_samplenums_tdo[-1][1] = self.samplenum

self.bits_tdi.insert(0, tdi)
self.bits_tdo.insert(0, tdo)
self.bits_tdi.append(tdi)
self.bits_tdo.append(tdo)

## Use self.samplenum as SS of the current bit.
self.bits_samplenums_tdi.insert(0, [self.samplenum, -1])
self.bits_samplenums_tdo.insert(0, [self.samplenum, -1])
self.bits_samplenums_tdi.append([self.samplenum, -1])
self.bits_samplenums_tdo.append([self.samplenum, -1])
## ----------------------------------------------------------------

self.data_ready = True
Expand All @@ -253,7 +253,10 @@ def handle_rising_tck_edge(self, tdi, tdo, tck, tms, trst, srst, rtck):
if self.data_ready:
self.data_ready = False
self.es_bitstring = self.samplenum

t = self.state[-2:] + ' TDI'
self.bits_tdi.reverse()
self.bits_samplenums_tdi.reverse()
b = ''.join(map(str, self.bits_tdi))
h = ' (0x%X' % int('0b' + b, 2) + ')'
s = t + ': ' + h + ', ' + str(len(self.bits_tdi)) + ' bits' #b +
Expand All @@ -265,6 +268,8 @@ def handle_rising_tck_edge(self, tdi, tdo, tck, tms, trst, srst, rtck):
self.bits_samplenums_tdi = []

t = self.state[-2:] + ' TDO'
self.bits_tdo.reverse()
self.bits_samplenums_tdo.reverse()
b = ''.join(map(str, self.bits_tdo))
h = ' (0x%X' % int('0b' + b, 2) + ')'
s = t + ': ' + h + ', ' + str(len(self.bits_tdo)) + ' bits' #+ b
Expand Down