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Unstable trailing edge of stopbit pulse while using software UPDI I/O #59
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Thank you. Yes actually I did that on purpose at the time for some reason it seemed like a good idea :P I think I will add your modification after some tests. |
Just an update, tests are progressing well, I've been able to reproduce your problem by using a 1k resistor and 500pF capacitance in the UPDI line. |
Thanks! I'm glad that my investigation could help somebody. [upd] I've understood why this happens in my programmer. I made high-voltage model (based on this schematics) that has Zener diode in UPDI circuit. It's 225pF of capacitance (and 1K resistor, yeah). Also BSS84 mosfet is connected to UPDI pin of programmer - 10 pF more (in series of 4.8K of resistance totally). |
I increased the capacitance until the problem appeared. It's an artificial experiment. But with the fix it can work even with 1nF :) so thanks. |
Under certain conditions, the software UART used for UPDI connection could fail, generating a "bad response to enter progmode command: RSP_ILLEGAL_MCU_STATE" error. For more details see this: #59 Thanks to https://github.com/kosilin for figuring out the cause of the problem and suggesting a fix.
Ok, I've updated the code. It's not exactly the same delay you used, but it should work. |
Thanks! I'll test the patch in few days. |
Cool. I'll close it then. |
Good day!
Earlier I spent some time trying to make working UPDI HV mini programmer that I'd made using slightly modified schematics. I'd investigated that updi_io_soft.cpp contains an error (at my sight) that leads to either unstable or completely failed programmer operating.
The problem is that at stop bit transmission UPDI pin is switched to input mode (line 225, updi_io_soft.cpp) just after it has set to "1" (line 214, updi_io_soft.cpp). The trailing edge of the stop bit might not be detected by target device due to very short positive pulse that is damping completely as a fact because of parasitic capacitances. I think it's an issue.
I suggest to add some delay after stop bit transmission. I'm not sure but it seems to be reasonable for me to append the same time as "0" pulse has (txdelay).
At least in my environment the modification has led to stable operating of my UPDI programmer.
This patch is included.
0001-Fixes-unstable-trailing-edge-of-stopbit-pulse-while-using-software-UPDI-IO.txt
Best regards,
Alexey
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