HW
- fixed bug in pipeline's RAW conflict detection when F ISA extension is disabled
- add RISC-V mcountinhibit CSR
- fixed bug in interrupt system; the external interrupt request lines of the CPU trigger now on rising edges
- update SPI module adding control options for automatic chip-select during block transfers
- add optional true-random number generator (TRNG) SoC sub-module
- add support for fence.tso instruction (executed as NOP)
- several rtl updates, cleanups and optimizations
- add CMOD A7 FPGA setup
- fix bug in JALR instruction decoding (offset generation)
SW
- fixed bug in generation of MEM files - initialization of certain sections was missing
- added missing sections to linker script
- made linker script memory layout configurable via makefile commands
- update default example program
Docu
- cleanup, rework and update of documentation
- update core complex block diagram