AHB2APB Bridge Formal Verification

Introduction

This repository contains all the materials related to the formal verification of an AHB2APB bridge, a critical component in SoC design facilitating communication between AHB and APB protocols. This project includes SystemVerilog assertions (SVA), Register Transfer Level (RTL) design files, a verification plan, and comprehensive documentation outlining the verification process and results.

Contents Overview

• ECE560_AHB2APB_Final_Report.pdf: The comprehensive final report detailing the verification process, results, and analysis.
• Project Progress Presentation.pdf: A presentation summarizing the project's progression and key findings.
• RTL/: Contains the RTL design files of the AHB2APB bridge.
• sva/: SystemVerilog assertions used for formal verification.
• specs_sheets/: Specifications and datasheets relevant to the AHB2APB bridge.
• Verification_Plan/: Documents outlining the planned verification strategies and methodologies.
• run/: Scripts and configurations used for running verification tests (Note: content may be ignored in Git tracking for privacy or size considerations).

Getting Started

To dive into the verification of the AHB2APB bridge, start by reviewing the ECE560_AHB2APB_Final_Report.pdf for a detailed understanding of the project's scope and findings. Explore the RTL/ and sva/ directories to examine the design and verification elements directly.

Contribution Guidelines

Contributions to enhance the verification process or improve the design are welcome. Please fork the repository and submit pull requests with your proposed changes. For major changes, kindly open an issue first to discuss what you would like to change.

the RTL was adopted from Public Repo: https://github.com/prajwalgekkouga