Material for the advanced physical design workshop
- Day 1 - Inception of open-source EDA, OpenLANE and Sky130 PDK
- Day 2 - Good floorplan vs bad floorplan and introduction to library cells
- Day 3 - Design library cell using Magic Layout and ngspice characterization
- Day 4 - Pre-layout timing analysis and importance of good clock tree
- Day 5 - Final steps for RTL2GDS
First, we look for the PDKs:
And for the libraries:
We use Openlane with Docker:
Preparing the project picorv32a
Checking reports:
Running Synthesis:
Checking Synthesis reports:
You can see some statistics related to the design
Checking the variables used in this stage:
floorplan.tcl:
config.tcl:
Running floorplan:
Checking in logs folder:
Checking .def file:
Then, we open Magic:
We continue with Placement
And the new layout:
First, we clone this repository https://github.com/nickson-jose/vsdstdcelldesign.git
Opening the inverter layout:
Checking the layout:
Generating a DRC error:
Extracting to spice:
Editing this document:
Running simulation with nspice:
Calculating rise, fall and propagation delay:
trise = 0.1356 ns tfall = 0.0508 ns PropDelay = 0.0606 ns
#4th Day
We edit and generate a .lef file from the last inverter:
To use them, we have to edit the config.tcl
Trying to improve timing:
