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FIRRTL
The FIRRTL (Flexible Intermediate Representation for RTL) Project provides a hardware circuit IR for posedge-triggered, synchronous or asynchronous reset-able, multi-clock domain, synchronous circuits, an optimizing compiler, a Verilog backend emitter, and a FIRRTL interpreter. The compiler is written in Scala. The language is easy to parse and ANTLR4 grammar is provided. Not all hardware constructs are supported (notably: negative edge triggered logic/#695), but Verilog blackboxing provides a temporary workaround while development of these features is in progress. FIRRTL provides support for Annotations: arbitrary metadata attached to specific circuit components. Annotations are not a part of the IR, but are passed along with the IR during compilation to direct and control FIRRTL transforms.
FIRRTL IR is the target of the Chisel language. Other front ends targeting the FIRRTL IR are available, e.g., Yosys and Magma.
- GIT: https://github.com/freechipsproject/firrtl
- License: BSD 3 Clause
- Internal representation: AST
- Optimization alg. paradigm: multi-paradigm (but most passes walk the AST, compute modifications, and then apply)
- FIRRTL IR Specification Document
- https://github.com/freechipsproject/firrtl/blob/master/src/main/scala/firrtl/ir/IR.scala
- The IR is simple, but additional provided analyses (Instance Graph, Circuit Graph) enable more complex views necessary for optimization/transformation