arm64: add more exception info to log outputs

HidenoriMatsubayashi · Aug 31, 2024 · 1a6a4d9 · 1a6a4d9
1 parent bbdfd2a
commit 1a6a4d9
Showing 1 changed file with 14 additions and 15 deletions.
diff --git a/src/arch/arm64/irq/trap.cc b/src/arch/arm64/irq/trap.cc
@@ -80,6 +80,11 @@ constexpr uint8_t kEsrEl2EcTrapFpReg = 0b000111;
 constexpr uint8_t kEsrEl2EcHvc64 = 0b010110;
 constexpr uint8_t kEsrEl2EcTrapSystem = 0b011000;
 constexpr uint8_t kEsrEl2EcTrapSve = 0b011001;
+// Instruction Abort from a lower Exception level.
+// Used for MMU faults generated by instruction accesses and
+// synchronous External aborts, including synchronous parity
+// or ECC errors. Not used for debug-related exceptions.
+[[maybe_unused]] constexpr uint8_t kEsrEl2EcInstructionAbortFromLow = 0b100000;
 constexpr uint8_t kEsrEl2EcDataAboartFromLow = 0b100100;
 
 constexpr uint8_t kIssTrappedMcrOrMrcAccessCp15 = 0b0010;
@@ -111,12 +116,9 @@ inline uint8_t EsrEl2Ec(uint64_t esr) {
   return ((esr >> kEsrEl2EcShift) & 0x3f);
 }
 
-inline bool TrapMcrMrcInstructions(Tcb* tsk,
-                                   const uint8_t opc2,
-                                   const uint8_t opc1,
-                                   const uint8_t crn,
-                                   const uint8_t rt,
-                                   const uint8_t crm,
+inline bool TrapMcrMrcInstructions(Tcb* tsk, const uint8_t opc2,
+                                   const uint8_t opc1, const uint8_t crn,
+                                   const uint8_t rt, const uint8_t crm,
                                    const uint8_t dir) {
 #define MSR(name, _op1, _crn, _crm, _op2)                                     \
   do {                                                                        \
@@ -173,7 +175,7 @@ inline bool TrapMcrMrcInstructions(Tcb* tsk,
 
     MRS(id_aa64mmfr0_el1, kOp1SCR, kCrnSCTLR_EL1, 7, 0);
     MRS(id_aa64mmfr1_el1, kOp1SCR, kCrnSCTLR_EL1, 7, 1);
-    //MRS(id_aa64mmfr2_el1, kOp1SCR, kCrnSCTLR_EL1, 7, 2);
+    // MRS(id_aa64mmfr2_el1, kOp1SCR, kCrnSCTLR_EL1, 7, 2);
     MRS(mpidr_el1, kOp1SCR, kCrnSCTLR_EL1, 7, 3);
 
     MRS(id_aa64afr0_el1, kOp1SCR, kCrnSCTLR_EL1, 5, 4);
@@ -283,7 +285,8 @@ inline uint8_t ESR_EL2_ISS_EXCEPTION_FROM_DATA_ABORT_WNR(uint64_t esr) {
   return (esr >> 6) & 0x1;
 }
 constexpr uint8_t kEsrEl2IssExceptionFromDataAboartCausedByRead = 0;
-[[maybe_unused]] constexpr uint8_t kEsrEl2IssExceptionFromDataAboartCausedByWrite = 1;
+[[maybe_unused]] constexpr uint8_t
+    kEsrEl2IssExceptionFromDataAboartCausedByWrite = 1;
 
 inline bool HandleTrapMemAbort(va_t addr, uint64_t esr) {
   const auto dfsc = ESR_EL2_ISS_EXCEPTION_FROM_DATA_ABORT_DFSC(esr);
@@ -309,9 +312,7 @@ inline bool HandleTrapMemAbort(va_t addr, uint64_t esr) {
 
 }  // namespace
 
-void TrapHandleLowerElAarch64Sync(uint64_t esr,
-                                  uint64_t elr,
-                                  uint64_t far,
+void TrapHandleLowerElAarch64Sync(uint64_t esr, uint64_t elr, uint64_t far,
                                   uint64_t hvc_nr) {
   const auto ec = EsrEl2Ec(esr);
   switch (ec) {
@@ -337,10 +338,8 @@ void TrapHandleLowerElAarch64Sync(uint64_t esr,
       }
       break;
     default:
-      PANIC(
-          "Uncaught exception: cause: %s, address: %x, far_el2: "
-          "%x",
-          kExceptionClass[ec], esr, elr, far);
+      PANIC("Uncaught exception(%d): cause: %s, address: %x, far_el2: %x", ec,
+            kExceptionClass[ec], esr, elr, far);
       break;
   }
 }