make connection to different execution stages

sim/hwdbg/DebuggerModuleTestingBRAM/Makefile

@@ -11,6 +11,7 @@ VERILOG_SOURCES += $(shell pwd)/../../../generated/DebuggerPacketInterpreter.sv
 VERILOG_SOURCES += $(shell pwd)/../../../generated/InterpreterSendVersion.sv
 VERILOG_SOURCES += $(shell pwd)/../../../generated/InterpreterSendError.sv
 VERILOG_SOURCES += $(shell pwd)/../../../generated/InterpreterPortInformation.sv
+VERILOG_SOURCES += $(shell pwd)/../../../generated/ScriptExecutionEngine.sv
 TOPLEVEL = DebuggerModuleTestingBRAM
 MODULE = test_DebuggerModuleTestingBRAM
 

src/main/scala/hwdbg/main.scala

@@ -22,6 +22,7 @@ import hwdbg.version._
 import hwdbg.configs._
 import hwdbg.types._
 import hwdbg.utils._
+import hwdbg.script._
 import hwdbg.communication._
 import hwdbg.communication.interpreter._
 
@@ -157,15 +158,30 @@ class DebuggerMain(
   sendWaitForBuffer := outSendWaitForBuffer
 
   // -----------------------------------------------------------------------
-  // Configure the output signals
+  // Create instance from script execution engine
   //
-  for (i <- 0 until numberOfPins) {
-    io.outputPin(i) := 0.U
-  }
+  val (outputPin) =
+    ScriptExecutionEngine(
+      debug,
+      numberOfPins,
+      maximumNumberOfStages,
+      bramAddrWidth,
+      bramDataWidth,
+      portsConfiguration
+    )(
+      io.en,
+      io.inputPin
+    )
 
+  // -----------------------------------------------------------------------
+  // Configure the output signals
+  //
   io.wrEna := wrEna
   io.wrData := wrData
   io.rdWrAddr := rdWrAddr
+
+  io.outputPin := outputPin
+
   io.psOutInterrupt := psOutInterrupt
 
 }

src/main/scala/hwdbg/script/exec.scala

@@ -13,15 +13,15 @@
  * @copyright
  *   This project is released under the GNU Public License v3.
  */
-package hwdbg.exec
+package hwdbg.script
 
 import chisel3._
 import chisel3.util._
 
 import hwdbg.configs._
 import hwdbg.stage._
 
-class ScriptExec(
+class ScriptExecutionEngine(
     debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
     numberOfPins: Int = DebuggerConfigurations.NUMBER_OF_PINS,
     maximumNumberOfStages: Int = DebuggerConfigurations.MAXIMUM_NUMBER_OF_STAGES,
@@ -66,14 +66,16 @@ class ScriptExec(
       // At the first stage, the input registers should be passed to the
       // first registers set of the stage registers
       //
-      stageRegs.pinValues(i) := io.inputPin
+      stageRegs.pinValues(i) := io.inputPin.asUInt
 
     } else if (i == (maximumNumberOfStages - 1)) {
 
       //
       // At the last stage, the state registers should be passed to the output
       //
-      outputPin := stageRegs.pinValues(i)
+      for (j <- 0 until numberOfPins) {
+        outputPin(j) := stageRegs.pinValues(i)(j)
+      }
 
     } else {
 
@@ -84,6 +86,7 @@ class ScriptExec(
       stageRegs.pinValues(i + 1) := stageRegs.pinValues(i)
     }
   }
+
   // -----------------------------------------------------------------------
 
   //
@@ -93,7 +96,7 @@ class ScriptExec(
 
 }
 
-object ScriptExec {
+object ScriptExecutionEngine {
 
   def apply(
       debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
@@ -107,8 +110,8 @@ object ScriptExec {
       inputPin: Vec[UInt]
   ): (Vec[UInt]) = {
 
-    val scriptExecModule = Module(
-      new ScriptExec(
+    val scriptExecutionEngineModule = Module(
+      new ScriptExecutionEngine(
         debug,
         numberOfPins,
         maximumNumberOfStages,
@@ -123,17 +126,17 @@ object ScriptExec {
     //
     // Configure the input signals
     //
-    scriptExecModule.io.en := en
-    scriptExecModule.io.inputPin := inputPin
+    scriptExecutionEngineModule.io.en := en
+    scriptExecutionEngineModule.io.inputPin := inputPin
 
     //
     // Configure the output signals
     //
-    outputPin := scriptExecModule.io.outputPin
+    outputPin := scriptExecutionEngineModule.io.outputPin
 
     //
     // Return the output result
     //
-    outputPin
+    (outputPin)
   }
 }