KLayout LVS rule deck (cross-platform compatibility) #179
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* Remove labels on ESD diodes so they are now recognized as regular d(p)antenna diodes * Increase width to minimum 0.48µm to account for new rule not yet in DRC check. Signed-off-by: Staf Verhaegen <staf.verhaegen@chipflow.io>
OpenROAD, OpenROAD flow scripts, Qucs-S added as supported EDA tools. Signed-off-by: Krzysztof Herman <141824113+KrzysztofHerman@users.noreply.github.com>
…nto dev Merging synced dev branch from own forc to local repo
-added partial implementation of class Pin from PyCell API -added partial implementation of class Term from PyCell API -added support for pins/terminals -added support for XOR geometric transformation -added support for text alignment/orientation -fixed dbLayerXorList from geometry.py -added support of npn13G2L and npn13G2V -extended documentation Signed-off-by: ThomasZecha <zecha@ihp-microelectronics.com>
Klayout PyCell integration
Some updates on top of #121
Signed-off-by: Daniel Arevalos <daniel.arevalos@sansano.usm.cl>
Signed-off-by: KrzysztofHerman <herman@ihp-microelectronics.com>
Signed-off-by: KrzysztofHerman <herman@ihp-microelectronics.com>
Layout rule manual update
Signed-off-by: FaragElsayed2 <farag_agoor@mabrains.com>
Removing NO DRC filter for LVS runset for all layers
Remove NO_DRC filtering
…V mosfets Signed-off-by: KrzysztofHerman <herman@ihp-microelectronics.com>
…m), symbols modified, some testcases modified Signed-off-by: KrzysztofHerman <herman@ihp-microelectronics.com>
-added PyCell parameter type bool -added partial implementation for PyCell API class Net -added partial implementation for PyCell API class Path -added partial implementation for PyCell API class ShapeFilter -added support for Net's -added generic registering of IHP PyCell's in Klayout -added support for inductor2, inductor2_sc, inductor2_sp, inductor3, inductor3_sc and inductor3_sp -updated documentation Signed-off-by: ThomasZecha <zecha@ihp-microelectronics.com>
-fixed merge-error Signed-off-by: ThomasZecha <zecha@ihp-microelectronics.com>
Klayout PyCell integration
Signed-off-by: Daniel Arevalos <daniel.arevalos@sansano.usm.cl>
…sistent w/ internal implementation Signed-off-by: Sergei Andreev <andreev@ihp-microelectronics.com>
Update path to standard symbols
Signed-off-by: KrzysztofHerman <herman@ihp-microelectronics.com>
NGSPICE model referencing based on .spiceinit
Signed-off-by: Sergei Andreev <andreev@ihp-microelectronics.com>
-Re-implemented clone() for shapes using deepcopy -Implemented tagging of shapes feature from SKILL Pcell counter-part -Fixed npn13G2L/npn13G2V to be equal to SKILL Pcell counter-part -Introduced library code/documentation as submodule from pycell4klayout-api repo Signed-off-by: ThomasZecha <zecha@ihp-microelectronics.com>
-simplified referencing python modules by setting search path Signed-off-by: ThomasZecha <zecha@ihp-microelectronics.com>
Klayout PyCell integration
Signed-off-by: Sergei Andreev <andreev@uxsrv002.ihp-ffo.de>
Signed-off-by: Sergei Andreev <andreev@ihp-microelectronics.com>
added requirement to set PDK_ROOT Signed-off-by: Sergei Andreev <116548619+sergeiandreyev@users.noreply.github.com>
Signed-off-by: Sergei Andreev <andreev@ihp-microelectronics.com>
Signed-off-by: Sergei Andreev <andreev@ihp-microelectronics.com>
Signed-off-by: Sergei Andreev <andreev@ihp-microelectronics.com>
Signed-off-by: Sergei Andreev <andreev@ihp-microelectronics.com>
- added note on current status - screenshot as an example Signed-off-by: Sergei Andreev <116548619+sergeiandreyev@users.noreply.github.com>
Krzysztof and Sergei are the maintainer of this repository. Add them as CODEOWNER to auto-assign them in Pull Requests. Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
The export.yml file communicates all exportable files, with additional meta data, to OpenROAD. It can automatically check if files changed or new exist and sync those. Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Add CODEOWNERS file
The .gitignore in the root level ignores directories like lib/. This will prevent checking in new libs as Git would ignore those. Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
libs.ref: Don't ignore sub-directories
Signed-off-by: Sergei Andreev <andreev@uxsrv002.ihp-ffo.de>
Signed-off-by: Sergei Andreev <andreev@ihp-microelectronics.com>
libs.ref: Python tool to generate export.yml
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I create another one using the standard work flow. |
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sg13g2_full.zip
Fixes #<issue_number_goes_here>
Added cross-platform compatibility for LVS rule deck.