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Gokul Kuppuswamy edited this page Sep 19, 2021
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- Caravel User Project Overview
- Architecture details of Caravel “harness” SoC
- Caravel Wishbone Demo
- Understanding Caravel GPIO
- Caravel user project features
- Efabless Caravel ASIC harness IRQ demo
- Open MPW Program - MPW-TWO Walkthrough
- [FOSSi Dial-Up] Mohamed Shalan - OpenLane, A Digital ASIC Flow for SkyWater 130nm Open PDK
- OpenLane Overview
- [FOSSi Dial-Up] Tim Ansell - Skywater PDK: Fully open source manufacturable PDK for a 130nm process
- Solid-State Circuits Directions Workshop: Democratizing IC Design
- VHDL to Verilog Conversion utility : https://github.com/pliu6/vhd2vl
- Complete Informative Spreadsheet