Releases: Infineon/capsense
release-v5.0.0
CAPSENSE™ Middleware Library 5.0
What is Included?
For a complete description of the CAPSENSE™ middleware, refer to README.md and API Reference Guide.
The revision history of the CAPSENSE™ middleware is also available at API Reference Guide Changelog.
The new support added in this release:
- The CAPSENSE™ fifth-generation LP device support
- The Inductive sensing (ISX) method support
- The Long Press gesture support
Known issues
| ID | Known Issue | Workaround |
|---|---|---|
| 319100 | GPIO simultaneous operation with unrestricted strength and frequency creates noise that can affect CAPSENSE™ operation. This issue is applicable for the fourth-generation CAPSENSE™ devices. | For detail, refer to the errata section of the device datasheet. |
| 3159 | Scanning a sensor with low capacitance (about 8pF and less) with low frequency (around 300kHz and less) might lead to raw count variation from scan to scan. This issue is applicable for the fourth-generation CAPSENSE™ devices. | There are several possible workarounds: 1. Increase the Scan resolution. 2. Increase the Sense clock frequency. For the best results, perform scanning with as high as possible Sense clock frequency. 3. If shield is required for a design, enable the shield tank (Csh) capacitor. 4. Increase the sensor capacitance by changing its layout or introduce extra capacitor between the sensor pin and ground. 5. Increase number of Fine initialization cycles. Open the cycfg_capsense.c file and modify the .csdFineInitTime field of the cy_capsense_commonConfig structure. 6. Increase the CSD init switch resistance. Open the cycfg_capsense.c file and update the .csdInitSwRes field of the cy_capsense_commonConfig structure with the CY_CAPSENSE_INIT_SW_RES_HIGH value. |
Note: Refer to the "Errata" section of the device datasheet to get information about the known problems related to the CAPSENSE™ HW IP block.
Supported software and tools
This version of the CAPSENSE™ middleware was validated for compatibility with the following software and tools:
| Software and tools | Version |
|---|---|
| ModusToolbox™ Software Environment | 3.2 |
| - ModusToolbox™ Device Configurator | 4.20 |
| - ModusToolbox™ MSC Superblock Personality for PSoC™ 4 devices in the Device Configurator | 1.0 |
| - ModusToolbox™ MSCLP Personality for PSoC™ 4 devices in the Device Configurator | 3.0 |
| - ModusToolbox™ MSC Personality for PSoC™ 4 devices in the Device Configurator | 1.1 |
| - ModusToolbox™ CSD Personality for PSoC™ 4 devices in the Device Configurator | 2.0 |
| - ModusToolbox™ CSD Personality for PSoC™ 6 devices in the Device Configurator | 3.0 |
| - ModusToolbox™ CAPSENSE™ Configurator / Tuner | 6.20 |
| CAT1 Peripheral Driver Library (PDL) | 3.9.0 |
| CAT2 Peripheral Driver Library (PDL) | 2.8.0 |
| GCC Compiler | 11.3.1 |
| IAR Compiler | 8.42.1 |
| ARM Compiler 6 | 6.13 |
| MBED OS | 5.15.8 |
| FreeRTOS | 10.4.5 |
Migration Guide
More information
For more information, refer to:
-
CAPSENSE™ overview:
-
ModusToolbox™ Overview:
-
Infineon Technologies AG Kits and Code Examples
- CAPSENSE™ Middleware Code Example for MBED OS
- CAPSENSE™ Middleware Code Example for FreeRTOS
- CY8CKIT-145-40XX PSoC™ 4000S CAPSENSE™ Prototyping Kit
- CY8CKIT-149 PSoC™ 4100S Plus Prototyping Kit
- CY8CKIT-041-40XX PSoC™ 4 S-Series Pioneer Kit
- CY8CKIT-041-41XX PSoC™ 4100S CAPSENSE™ Pioneer Kit
- CY8CKIT-040T PSoC™ 4000T CAPSENSE™ Evaluation Kit
-
General information:
- AN210781 Getting Started with PSoC™ 6 MCU with Bluetooth Low Energy (BLE) Connectivity
- AN215671 PSoC™ 6 MCU firmware design for BLE applications
- PSoC™ 6 Technical Reference Manual
- PSoC™ 63 with BLE Datasheet Programmable System-on-Chip datasheet
- CAT1 PDL API Reference
- CAT2 PDL API Reference
- PSoC™ 4000S Family: PSoC™ 4 Architecture Technical Reference Manual (TRM)
- PSoC™ 4100S and PSoC™ 4100S Plus: PSoC™ 4 Architecture Technical Reference Manual (TRM)
- Infineon Technologies GitHub
- Infineon Technologies
© 2020-2024, Cypress Semiconductor Corporation (an Infineon company) or an affiliate of Cypress Semiconductor Corporation.
CAPSENSE™ Middleware Library 4.0
What is Included?
For a complete description of the CAPSENSE™ middleware, refer to README.md and API Reference Guide.
The revision history of the CAPSENSE™ middleware is also available at API Reference Guide Changelog.
The new support added in this release:
- The CAPSENSE™ fifth-generation LP device support
- The Inductive sensing (ISX) method support
- The Long Press gesture support
Known issues
| ID | Known Issue | Workaround |
|---|---|---|
| 319100 | GPIO simultaneous operation with unrestricted strength and frequency creates noise that can affect CAPSENSE™ operation. This issue is applicable for the fourth-generation CAPSENSE™ devices. | For detail, refer to the errata section of the device datasheet. |
| 3159 | Scanning a sensor with low capacitance (about 8pF and less) with low frequency (around 300kHz and less) might lead to raw count variation from scan to scan. This issue is applicable for the fourth-generation CAPSENSE™ devices. | There are several possible workarounds: 1. Increase the Scan resolution. 2. Increase the Sense clock frequency. For the best results, perform scanning with as high as possible Sense clock frequency. 3. If shield is required for a design, enable the shield tank (Csh) capacitor. 4. Increase the sensor capacitance by changing its layout or introduce extra capacitor between the sensor pin and ground. 5. Increase number of Fine initialization cycles. Open the cycfg_capsense.c file and modify the .csdFineInitTime field of the cy_capsense_commonConfig structure. 6. Increase the CSD init switch resistance. Open the cycfg_capsense.c file and update the .csdInitSwRes field of the cy_capsense_commonConfig structure with the CY_CAPSENSE_INIT_SW_RES_HIGH value. |
| 11742 | Use of Multi-phase scanning with Self-Cap method CSD (MPSC) causes high noise of sensors and/or can lead to hanging the CAPSENSE™ solution. This issue is applicable for the fifth-generation low power CAPSENSE™ devices. | Do not use this method by setting the Multi-phase self order parameter to 1. |
| 11743 | The CDAC auto-calibration algorithm does not use the full range of Fine CDAC codes. It leads to incorrect auto-calibration when operating in a transition condition (Reference CDAC value<=6) between Reference CDAC and Fine CDAC. This issue is applicable for the fifth-generation low power CAPSENSE™ devices. | Disable Fine CDAC. (Note: it is recommended to enable Fine CDAC if calibrated Reference CDAC value <=6). If operating in a condition as mentioned, increase auto-calibrated Reference CDAC code as follows: - Increase Sense Clock Frequency (decrease the Sense clock divider parameter) and correspondingly reduce series resistance for shield electrode (for CSD RM) or Tx/Rx electrodes (CSX RM) to ensure each clock phase still has 5Tau settling. - Disable Compensation CDAC. - Increase sensor Cp physically, or by disabling shield, or setting the Inactive sensor connection parameter to ground. |
Supported software and tools
This version of the CAPSENSE™ middleware was validated for compatibility with the following software and tools:
| Software and tools | Version |
|---|---|
| ModusToolbox™ Software Environment | 3.1 |
| - ModusToolbox™ Device Configurator | 4.10 |
| - ModusToolbox™ MSC Superblock Personality for PSoC™ 4 devices in the Device Configurator | 1.0 |
| - ModusToolbox™ MSCLP Personality for PSoC™ 4 devices in the Device Configurator | 3.0 |
| - ModusToolbox™ MSC Personality for PSoC™ 4 devices in the Device Configurator | 1.1 |
| - ModusToolbox™ CSD Personality for PSoC™ 4 devices in the Device Configurator | 2.0 |
| - ModusToolbox™ CSD Personality for PSoC™ 6 devices in the Device Configurator | 2.0 |
| - ModusToolbox™ CAPSENSE™ Configurator / Tuner | 6.10 |
| CAT1 Peripheral Driver Library (PDL) | 3.3.1 |
| CAT2 Peripheral Driver Library (PDL) | 2.5.0 |
| GCC Compiler | 11.3.1 |
| IAR Compiler | 8.42.1 |
| ARM Compiler 6 | 6.13 |
| MBED OS | 5.15.8 |
| FreeRTOS | 10.4.5 |
More information
For more information, refer to:
-
CAPSENSE™ overview:
-
ModusToolbox™ Overview:
-
Infineon Technologies AG Kits and Code Examples
-
General information:
- AN210781 Getting Started with PSoC™ 6 MCU with Bluetooth Low Energy (BLE) Connectivity
- PSoC™ 6 Technical Reference Manual
- PSoC™ 63 with BLE Datasheet Programmable System-on-Chip datasheet
- CAT1 PDL API Reference
- CAT2 PDL API Reference
- PSoC™ 4000S Family: PSoC™ 4 Architecture Technical Reference Manual (TRM)
- PSoC™ 4100S and PSoC™ 4100S Plus: PSoC™ 4 Architecture Technical Reference Manual (TRM)
- Infineon Technologies GitHub
- Infineon Technologies
CYPRESS™ Semiconductor Corporation, 2019-2023.
CapSense Middleware 3.0.1 Release
CAPSENSE™ Middleware Library 3.0.1
What's Included?
Please refer to the README.md and the API Reference Guide for a complete description of the CAPSENSE™ Middleware.
The revision history of the CAPSENSE™ Middleware is also available on the API Reference Guide Changelog.
New important things in this release:
- Added CAPSENSE™ fifth-generation device support
- Added flash memory optimization
Known Issues
Refer to the API Reference Guide - Errata section for a complete description of the known issues and possible workarounds
Supported Software and Tools
This version of the CAPSENSE™ Middleware was validated for compatibility with the following Software and Tools:
| Software and Tools | Version |
|---|---|
| ModusToolbox™ Software Environment | 3.0 |
| - ModusToolbox™ Device Configurator | 4.0 |
| - ModusToolbox™ MSC Superblock Personality for for PSoC™ 4 devices in the Device Configurator | 1.0 |
| - ModusToolbox™ MSC Personality for PSoC™ 4 devices in Device Configurator | 1.1 |
| - ModusToolbox™ CSD Personality for PSoC™ 4 devices in Device Configurator | 2.0 |
| - ModusToolbox™ CSD Personality for PSoC™ 6 devices in Device Configurator | 3.0 |
| - ModusToolbox™ CAPSENSE™ Configurator / Tuner tools | 5.0.0 |
| CAT1 Peripheral Driver Library (PDL) | 3.0.0 |
| CAT2 Peripheral Driver Library (PDL) | 2.0.0 |
| GCC Compiler | 10.3.1 |
| IAR Compiler | 8.42.1 |
| ARM Compiler 6 | 6.13 |
| MBED OS | 5.15.8 |
| FreeRTOS | 10.4.5 |
More information
The following resources contain more information:
- CAPSENSE™ Overview:
- ModusToolbox™ Overview:
- Infineon Technologies Kits and Code Examples:
- General information:
- AN210781 Getting Started with PSoC™ 6 MCU with Bluetooth Low Energy (BLE) Connectivity
- PSoC™ 6 Technical Reference Manual
- PSoC™ 63 with BLE Datasheet Programmable System-on-Chip datasheet
- CAT1 PDL API Reference
- CAT2 PDL API Reference
- PSoC™ 4000S Family: PSoC™ 4 Architecture Technical Reference Manual (TRM)
- PSoC™ 4100S and PSoC™ 4100S Plus: PSoC™ 4 Architecture Technical Reference Manual (TRM)
- Infineon Technologies GitHub
- Infineon Technologies
CYPRESS™ Semiconductor Corporation, 2019-2023.
CAPSENSE™ Middleware Library 4.0 (Preliminary)
What is Included?
For a complete description of the CAPSENSE™ middleware, refer to README.md and API Reference Guide.
The revision history of the CAPSENSE™ middleware is also available at API Reference Guide Changelog.
The new support added in this release:
- The CAPSENSE™ fifth-generation LP device support
- The Inductive sensing (ISX) method support
Known issues
For a complete description of the known issues and possible workarounds, refer to the API Reference Guide - Errata section.
Supported software and tools
This version of the CAPSENSE™ middleware was validated for compatibility with the following software and tools:
| Software and tools | Version |
|---|---|
| ModusToolbox™ Software Environment | 3.0 |
| - ModusToolbox™ Device Configurator | 3.20 |
| - ModusToolbox™ MSC Superblock Personality for for PSoC™ 4 devices in the Device Configurator | 1.0 |
| - ModusToolbox™ MSCLP Personality for PSoC™ 4 devices in the Device Configurator | 1.0 |
| - ModusToolbox™ MSC Personality for PSoC™ 4 devices in the Device Configurator | 1.1 |
| - ModusToolbox™ CSD Personality for PSoC™ 4 devices in the Device Configurator | 1.2 |
| - ModusToolbox™ CSD Personality for PSoC™ 6 devices in the Device Configurator | 2.0 |
| - ModusToolbox™ CAPSENSE™ Configurator / Tuner | 5.0 |
| CAT1 Peripheral Driver Library (PDL) | 2.3.0 |
| CAT2 Peripheral Driver Library (PDL) | 2.0.0 |
| GCC Compiler | 10.3.1 |
| IAR Compiler | 8.42.1 |
| ARM Compiler 6 | 6.13 |
| MBED OS | 5.15.8 |
| FreeRTOS | 10.4.5 |
More information
For more information, refer to:
- CAPSENSE™ overview:
- ModusToolbox™ overview:
- Infineon Technologies AG kits and code examples:
- General information:
- AN210781 Getting Started with PSoC™ 6 MCU with Bluetooth Low Energy (BLE) Connectivity
- PSoC™ 6 Technical Reference Manual
- PSoC™ 63 with BLE Datasheet Programmable System-on-Chip datasheet
- CAT1 PDL API Reference
- CAT2 PDL API Reference
- PSoC™ 4000S Family: PSoC™ 4 Architecture Technical Reference Manual (TRM)
- PSoC™ 4100S and PSoC™ 4100S Plus: PSoC™ 4 Architecture Technical Reference Manual (TRM)
- Infineon Technologies GitHub
- Infineon Technologies
CYPRESS™ Semiconductor Corporation, 2019-2022.
CapSense Middleware 3.0 Release
What's Included?
Please refer to the README.md and the API Reference Guide for a complete description of the CAPSENSE™ Middleware.
The revision history of the CAPSENSE™ Middleware is also available on the API Reference Guide Changelog.
New important things in this release:
- Added CAPSENSE™ fifth-generation device support
- Added flash memory optimization
Known Issues
Refer to the API Reference Guide - Errata section for a complete description of the known issues and possible workarounds
Supported Software and Tools
This version of the CAPSENSE™ Middleware was validated for compatibility with the following Software and Tools:
| Software and Tools | Version |
|---|---|
| ModusToolbox™ Software Environment | 2.4 |
| - ModusToolbox™ Device Configurator | 3.10 |
| - ModusToolbox™ MSC Superblock Personality for for PSoC™ 4 devices in the Device Configurator | 1.0 |
| - ModusToolbox™ MSC Personality for PSoC™ 4 devices in Device Configurator | 1.1 |
| - ModusToolbox™ CSD Personality for PSoC™ 4 devices in Device Configurator | 1.1 |
| - ModusToolbox™ CSD Personality for PSoC™ 6 devices in Device Configurator | 2.0 |
| - ModusToolbox™ CAPSENSE™ Configurator / Tuner tools | 4.0 |
| CAT1 Peripheral Driver Library (PDL) | 2.3.0 |
| CAT2 Peripheral Driver Library (PDL) | 1.4.0 |
| GCC Compiler | 10.3.1 |
| IAR Compiler | 8.42.1 |
| ARM Compiler 6 | 6.13 |
| MBED OS | 5.15.8 |
| FreeRTOS | 10.4.5 |
More information
The following resources contain more information:
- CAPSENSE™ Overview:
- ModusToolbox™ Overview:
- Infineon Technologies Kits and Code Examples:
- General Information:
- AN210781 Getting Started with PSoC™ 6 MCU with Bluetooth Low Energy (BLE) Connectivity
- PSoC™ 6 Technical Reference Manual
- PSoC™ 63 with BLE Datasheet Programmable System-on-Chip datasheet
- CAT1 PDL API Reference
- CAT2 PDL API Reference
- PSoC™ 4000S Family: PSoC™ 4 Architecture Technical Reference Manual (TRM)
- PSoC™ 4100S and PSoC™ 4100S Plus: PSoC™ 4 Architecture Technical Reference Manual (TRM)
- Infineon Technologies GitHub
- Infineon Technologies
CYPRESS™ Semiconductor Corporation, 2019-2021.
CapSense Middleware 2.10 Release
What's Included?
Please refer to the README.md and the API Reference Guide for a complete description of the CapSense Middleware.
The revision history of the CapSense Middleware is also available on the API Reference Guide Changelog.
New in this release:
- Added Built-in Self-test (BIST) library to support Class B (IEC-60730), safety integrity-level compliant design
Known Issues
Refer to the errata section of the capsense API reference manual:
Supported Software and Tools
This version of the CapSense Middleware was validated for compatibility with the following Software and Tools:
| Software and Tools | Version |
|---|---|
| ModusToolbox Software Environment | 2.1 |
| - ModusToolbox Device Configurator | 2.1 |
| - ModusToolbox CSD Personality for PSoC4 devices in Device Configurator | 1.0 |
| - ModusToolbox CSD Personality for PSoC6 devices in Device Configurator | 2.0 |
| - ModusToolbox CapSense Configurator / Tuner tools | 3.0 |
| PSoC6 Peripheral Driver Library (PDL) | 1.5.0 |
| GCC Compiler | 7.2.1 |
| IAR Compiler | 8.32 |
| ARM Compiler 6 | 6.11 |
| MBED OS | 5.15.1 |
| FreeRTOS | 10.0.1 |
More information
The following resources contain more information:
- CapSense Middleware README.md
- CapSense Middleware API Reference Guide
- ModusToolbox Software Environment, Quick Start Guide, Documentation, and Videos
- CapSense Middleware Code Example for MBED OS
- CapSense Middleware Code Example for FreeRTOS
- CapSense Middleware Code Examples at GITHUB
- ModusToolbox CapSense Configurator Tool Guide
- ModusToolbox CapSense Tuner Tool Guide
- ModusToolbox Device Configurator Tool Guide
- CapSense Design Guide
- CSDADC Middleware API Reference Guide
- CSDIDAC Middleware API Reference Guide
- AN210781 Getting Started with PSoC 6 MCU with Bluetooth Low Energy (BLE) Connectivity
- PSoC 6 Technical Reference Manual
- PSoC 63 with BLE Datasheet Programmable System-on-Chip datasheet
- Cypress Semiconductor
© Cypress Semiconductor Corporation, 2019-2020.
CapSense Middleware 2.0 Release
New in this release:
- Optimized flash memory consumption based on user's configuration
- Added the memory usage section
- Added the errata section
Known Issues
| Problem | Workaround |
|---|---|
| GPIO simultaneous operation with unrestricted strength and frequency creates noise that can affect CapSense operation | Refer to the errata section of the device datasheet for details |
Defect Fixes
- Renamed function Cy_CapSense_CheckCommandIntegrity() to Cy_CapSense_CheckTunerCmdIntegrity()
- Fixing a compilation error for non CapSense-capable devices: CapSense MW sources are enclosed with the conditional compilation
See the RELEASE.md file for known issues and links to other resources.
CapSense Middleware 1.20 Release
Added ARMC6 compiler support. Changed the hierarchy of the binary files folder for MbedOS compatibility. Added the CapSense API reference documentation to the repo.
See the RELEASE.md file for known issues and links to other resources.
CapSense Middleware 1.1 Release
Initial commit of CapSense middleware