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Upload mtb-example-usb-device-cdc-echo [796]
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gitlab-runner committed Mar 8, 2023
1 parent 90b27d3 commit 341e52c
Showing 13 changed files with 1,073 additions and 141 deletions.
2 changes: 1 addition & 1 deletion Makefile
Original file line number Diff line number Diff line change
@@ -7,7 +7,7 @@
#
################################################################################
# \copyright
# Copyright 2018-2022, Cypress Semiconductor Corporation (an Infineon company)
# Copyright 2018-2023, Cypress Semiconductor Corporation (an Infineon company)
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
98 changes: 49 additions & 49 deletions README.md

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879 changes: 879 additions & 0 deletions templates/TARGET_CY8CEVAL-062S2-LAI-43439M2/config/design.modus

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19 changes: 16 additions & 3 deletions templates/TARGET_CY8CEVAL-062S2-LAI-4373M2/config/design.modus
Original file line number Diff line number Diff line change
@@ -396,6 +396,7 @@
<Block location="ioss[0].port[7].pin[0]">
<Alias value="CYBSP_LED_RGB_RED"/>
<Alias value="CYBSP_USER_LED3"/>
<Alias value="CYBSP_TRACE_CLK"/>
</Block>
<Block location="ioss[0].port[7].pin[1]">
<Alias value="CYBSP_CINA"/>
@@ -567,18 +568,22 @@
<Block location="ioss[0].port[9].pin[0]">
<Alias value="CYBSP_A8"/>
<Alias value="CYBSP_J2_2"/>
<Alias value="CYBSP_TRACE_DATA3"/>
</Block>
<Block location="ioss[0].port[9].pin[1]">
<Alias value="CYBSP_A9"/>
<Alias value="CYBSP_J2_4"/>
<Alias value="CYBSP_TRACE_DATA2"/>
</Block>
<Block location="ioss[0].port[9].pin[2]">
<Alias value="CYBSP_A10"/>
<Alias value="CYBSP_J2_6"/>
<Alias value="CYBSP_TRACE_DATA1"/>
</Block>
<Block location="ioss[0].port[9].pin[3]">
<Alias value="CYBSP_A11"/>
<Alias value="CYBSP_J2_8"/>
<Alias value="CYBSP_TRACE_DATA0"/>
</Block>
<Block location="ioss[0].port[9].pin[4]">
<Alias value="CYBSP_A12"/>
@@ -606,16 +611,24 @@
<Param id="startOnReset" value="true"/>
</Personality>
</Block>
<Block location="peri[0].div_16[15]">
<Personality template="pclk" version="3.0">
<Param id="intDivider" value="1"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Personality>
</Block>
<Block location="peri[0].div_8[0]">
<Alias value="CYBSP_CSD_CLK_DIV"/>
<Alias value="CYBSP_CS_CLK_DIV"/>
<Personality template="pclk" version="3.0">
<Param id="intDivider" value="256"/>
<Param id="intDivider" value="1"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Personality>
</Block>
<Block location="peri[0].div_8[3]">
<Block location="peri[0].div_8[7]">
<Alias value="CYBSP_TRACE_CLK_DIV"/>
<Personality template="pclk" version="3.0">
<Param id="intDivider" value="1"/>
<Param id="fracDivider" value="0"/>
@@ -766,7 +779,7 @@
<Netlist>
<Net>
<Port name="cpuss[0].dap[0].clock_trace_in[0]"/>
<Port name="peri[0].div_8[3].clk[0]"/>
<Port name="peri[0].div_8[7].clk[0]"/>
</Net>
<Net>
<Port name="cpuss[0].dap[0].swj_swclk_tclk[0]"/>
18 changes: 16 additions & 2 deletions templates/TARGET_CY8CEVAL-062S2-MUR-43439M2/config/design.modus
Original file line number Diff line number Diff line change
@@ -396,6 +396,7 @@
<Block location="ioss[0].port[7].pin[0]">
<Alias value="CYBSP_LED_RGB_RED"/>
<Alias value="CYBSP_USER_LED3"/>
<Alias value="CYBSP_TRACE_CLK"/>
</Block>
<Block location="ioss[0].port[7].pin[1]">
<Alias value="CYBSP_CINA"/>
@@ -567,18 +568,22 @@
<Block location="ioss[0].port[9].pin[0]">
<Alias value="CYBSP_A8"/>
<Alias value="CYBSP_J2_2"/>
<Alias value="CYBSP_TRACE_DATA3"/>
</Block>
<Block location="ioss[0].port[9].pin[1]">
<Alias value="CYBSP_A9"/>
<Alias value="CYBSP_J2_4"/>
<Alias value="CYBSP_TRACE_DATA2"/>
</Block>
<Block location="ioss[0].port[9].pin[2]">
<Alias value="CYBSP_A10"/>
<Alias value="CYBSP_J2_6"/>
<Alias value="CYBSP_TRACE_DATA1"/>
</Block>
<Block location="ioss[0].port[9].pin[3]">
<Alias value="CYBSP_A11"/>
<Alias value="CYBSP_J2_8"/>
<Alias value="CYBSP_TRACE_DATA0"/>
</Block>
<Block location="ioss[0].port[9].pin[4]">
<Alias value="CYBSP_A12"/>
@@ -606,6 +611,13 @@
<Param id="startOnReset" value="true"/>
</Personality>
</Block>
<Block location="peri[0].div_16[15]">
<Personality template="pclk" version="3.0">
<Param id="intDivider" value="1"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Personality>
</Block>
<Block location="peri[0].div_8[0]">
<Alias value="CYBSP_CSD_CLK_DIV"/>
<Alias value="CYBSP_CS_CLK_DIV"/>
@@ -615,7 +627,8 @@
<Param id="startOnReset" value="true"/>
</Personality>
</Block>
<Block location="peri[0].div_8[3]">
<Block location="peri[0].div_8[7]">
<Alias value="CYBSP_TRACE_CLK_DIV"/>
<Personality template="pclk" version="3.0">
<Param id="intDivider" value="1"/>
<Param id="fracDivider" value="0"/>
@@ -647,6 +660,7 @@
<Personality template="fll" version="4.0">
<Param id="configuration" value="auto"/>
<Param id="desiredFrequency" value="100.000"/>
<Param id="enableOutputDivider" value="false"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].hfclk[0]">
@@ -766,7 +780,7 @@
<Netlist>
<Net>
<Port name="cpuss[0].dap[0].clock_trace_in[0]"/>
<Port name="peri[0].div_8[3].clk[0]"/>
<Port name="peri[0].div_8[7].clk[0]"/>
</Net>
<Net>
<Port name="cpuss[0].dap[0].swj_swclk_tclk[0]"/>
17 changes: 15 additions & 2 deletions templates/TARGET_CY8CEVAL-062S2/config/design.modus
Original file line number Diff line number Diff line change
@@ -396,6 +396,7 @@
<Block location="ioss[0].port[7].pin[0]">
<Alias value="CYBSP_LED_RGB_RED"/>
<Alias value="CYBSP_USER_LED3"/>
<Alias value="CYBSP_TRACE_CLK"/>
</Block>
<Block location="ioss[0].port[7].pin[1]">
<Alias value="CYBSP_CINA"/>
@@ -567,18 +568,22 @@
<Block location="ioss[0].port[9].pin[0]">
<Alias value="CYBSP_A8"/>
<Alias value="CYBSP_J2_2"/>
<Alias value="CYBSP_TRACE_DATA3"/>
</Block>
<Block location="ioss[0].port[9].pin[1]">
<Alias value="CYBSP_A9"/>
<Alias value="CYBSP_J2_4"/>
<Alias value="CYBSP_TRACE_DATA2"/>
</Block>
<Block location="ioss[0].port[9].pin[2]">
<Alias value="CYBSP_A10"/>
<Alias value="CYBSP_J2_6"/>
<Alias value="CYBSP_TRACE_DATA1"/>
</Block>
<Block location="ioss[0].port[9].pin[3]">
<Alias value="CYBSP_A11"/>
<Alias value="CYBSP_J2_8"/>
<Alias value="CYBSP_TRACE_DATA0"/>
</Block>
<Block location="ioss[0].port[9].pin[4]">
<Alias value="CYBSP_A12"/>
@@ -606,6 +611,13 @@
<Param id="startOnReset" value="true"/>
</Personality>
</Block>
<Block location="peri[0].div_16[15]">
<Personality template="pclk" version="3.0">
<Param id="intDivider" value="1"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Personality>
</Block>
<Block location="peri[0].div_8[0]">
<Alias value="CYBSP_CSD_CLK_DIV"/>
<Alias value="CYBSP_CS_CLK_DIV"/>
@@ -615,7 +627,8 @@
<Param id="startOnReset" value="true"/>
</Personality>
</Block>
<Block location="peri[0].div_8[3]">
<Block location="peri[0].div_8[7]">
<Alias value="CYBSP_TRACE_CLK_DIV"/>
<Personality template="pclk" version="3.0">
<Param id="intDivider" value="1"/>
<Param id="fracDivider" value="0"/>
@@ -766,7 +779,7 @@
<Netlist>
<Net>
<Port name="cpuss[0].dap[0].clock_trace_in[0]"/>
<Port name="peri[0].div_8[3].clk[0]"/>
<Port name="peri[0].div_8[7].clk[0]"/>
</Net>
<Net>
<Port name="cpuss[0].dap[0].swj_swclk_tclk[0]"/>
26 changes: 24 additions & 2 deletions templates/TARGET_CY8CKIT-062-WIFI-BT/config/design.modus
Original file line number Diff line number Diff line change
@@ -357,6 +357,9 @@
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[7].pin[0]">
<Alias value="CYBSP_TRACE_CLK"/>
</Block>
<Block location="ioss[0].port[7].pin[1]">
<Alias value="CYBSP_CINA"/>
<Personality template="pin" version="3.0">
@@ -387,6 +390,15 @@
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[7].pin[4]">
<Alias value="CYBSP_TRACE_DATA3"/>
</Block>
<Block location="ioss[0].port[7].pin[5]">
<Alias value="CYBSP_TRACE_DATA2"/>
</Block>
<Block location="ioss[0].port[7].pin[6]">
<Alias value="CYBSP_TRACE_DATA1"/>
</Block>
<Block location="ioss[0].port[7].pin[7]">
<Alias value="CYBSP_CMOD"/>
<Personality template="pin" version="3.0">
@@ -529,6 +541,7 @@
<Block location="ioss[0].port[9].pin[3]">
<Alias value="CYBSP_A11"/>
<Alias value="CYBSP_J2_8"/>
<Alias value="CYBSP_TRACE_DATA0"/>
</Block>
<Block location="ioss[0].port[9].pin[4]">
<Alias value="CYBSP_A12"/>
@@ -549,7 +562,7 @@
<Param id="startOnReset" value="true"/>
</Personality>
</Block>
<Block location="peri[0].div_8[1]">
<Block location="peri[0].div_16[15]">
<Personality template="pclk" version="3.0">
<Param id="intDivider" value="1"/>
<Param id="fracDivider" value="0"/>
@@ -565,6 +578,14 @@
<Param id="startOnReset" value="true"/>
</Personality>
</Block>
<Block location="peri[0].div_8[7]">
<Alias value="CYBSP_TRACE_CLK_DIV"/>
<Personality template="pclk" version="3.0">
<Param id="intDivider" value="1"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Personality>
</Block>
<Block location="srss[0].clock[0]">
<Personality template="sysclocks" version="3.0"/>
</Block>
@@ -590,6 +611,7 @@
<Personality template="fll" version="4.0">
<Param id="configuration" value="auto"/>
<Param id="desiredFrequency" value="100.000"/>
<Param id="enableOutputDivider" value="false"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].hfclk[0]">
@@ -704,7 +726,7 @@
<Netlist>
<Net>
<Port name="cpuss[0].dap[0].clock_trace_in[0]"/>
<Port name="peri[0].div_8[1].clk[0]"/>
<Port name="peri[0].div_8[7].clk[0]"/>
</Net>
<Net>
<Port name="cpuss[0].dap[0].swj_swclk_tclk[0]"/>
21 changes: 19 additions & 2 deletions templates/TARGET_CY8CKIT-062S2-43012/config/design.modus
Original file line number Diff line number Diff line change
@@ -368,6 +368,9 @@
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[7].pin[0]">
<Alias value="CYBSP_TRACE_CLK"/>
</Block>
<Block location="ioss[0].port[7].pin[1]">
<Alias value="CYBSP_CINA"/>
<Personality template="pin" version="3.0">
@@ -402,11 +405,16 @@
<Alias value="CYBSP_LED_RGB_BLUE"/>
<Alias value="CYBSP_USER_LED5"/>
</Block>
<Block location="ioss[0].port[7].pin[4]">
<Alias value="CYBSP_TRACE_DATA3"/>
</Block>
<Block location="ioss[0].port[7].pin[5]">
<Alias value="CYBSP_D8"/>
<Alias value="CYBSP_TRACE_DATA2"/>
</Block>
<Block location="ioss[0].port[7].pin[6]">
<Alias value="CYBSP_D9"/>
<Alias value="CYBSP_TRACE_DATA1"/>
</Block>
<Block location="ioss[0].port[7].pin[7]">
<Alias value="CYBSP_CMOD"/>
@@ -550,6 +558,7 @@
<Block location="ioss[0].port[9].pin[3]">
<Alias value="CYBSP_A11"/>
<Alias value="CYBSP_J2_8"/>
<Alias value="CYBSP_TRACE_DATA0"/>
</Block>
<Block location="ioss[0].port[9].pin[4]">
<Alias value="CYBSP_A12"/>
@@ -573,6 +582,13 @@
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Personality>
</Block>
<Block location="peri[0].div_16[15]">
<Personality template="pclk" version="3.0">
<Param id="intDivider" value="1"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Personality>
</Block>
<Block location="peri[0].div_8[0]">
<Alias value="CYBSP_CSD_CLK_DIV"/>
@@ -583,7 +599,8 @@
<Param id="startOnReset" value="true"/>
</Personality>
</Block>
<Block location="peri[0].div_8[3]">
<Block location="peri[0].div_8[7]">
<Alias value="CYBSP_TRACE_CLK_DIV"/>
<Personality template="pclk" version="3.0">
<Param id="intDivider" value="1"/>
<Param id="fracDivider" value="0"/>
@@ -734,7 +751,7 @@
<Netlist>
<Net>
<Port name="cpuss[0].dap[0].clock_trace_in[0]"/>
<Port name="peri[0].div_8[3].clk[0]"/>
<Port name="peri[0].div_8[7].clk[0]"/>
</Net>
<Net>
<Port name="cpuss[0].dap[0].swj_swclk_tclk[0]"/>
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