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15 changes: 4 additions & 11 deletions RELEASE.md
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# MTB CAT1 Peripheral Driver Library v3.12.0
# MTB CAT1 Peripheral Driver Library v3.12.1

Please refer to the [README.md](./README.md) and the
[PDL API Reference Manual](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/index.html)
for a complete description of the Peripheral Driver Library.


## Implementation Details
* CAT1C: This release enables D-CACHE on CAT1C platform by default. To disable, define flag CY_DISABLE_XMC7000_DATA_CACHE
in Makefile. With this feature enabled, application need to take care of Data Cache Coherency by cleaning (after write) and invalidating (before read).
* Personality re-structuring: Personality supporting Schema v9 added. Personalities_9.0 is a copy of ‘personalities_8.0’ with
needed personalities updated to use schema v9. These personalities are available in folder device-info/personalities_9.0. Personalities supporting schema v9 are visible in MTB 3.2. For backward compatibility with MTB 3.0 and MTB 3.1, this release will also have older personalities in folder device-info/personalities.
* CAT1A: Support for EZ-USB FX3G2 devices: cyusb4xxx, cyusb3xxx, cyusb2xxx


## Build Changes
Expand All @@ -19,15 +16,11 @@ for a complete description of the Peripheral Driver Library.
## Added Drivers

## Updated Drivers
* [CRYPTO 2.120](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__crypto.html)
* [SMIF 2.90](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__smif.html)

### Drivers with patch version updates


### Obsoleted part numbers


## Known Issues
* CAT1A: In device-configurator, certain IP is not completely available for some devices as some combinations of pin connections are not valid.
* CYT2BL4BAS/CYT2BL4CAE: SCB6 is complete only for UART, cannot support I2C, EZI2C, or SPI.
Expand Down Expand Up @@ -59,9 +52,9 @@ This version of PDL was validated for compatibility with the following Software
| CMSIS | 5.8.1 |
| GCC Compiler | 11.3.1 |
| IAR Compiler | 9.40.2 |
| ARM Compiler 6 | 6.16 |
| ARM Compiler 6 | 6.22 |
| FreeRTOS | 10.4.305 |
| [Device Database](https://github.com/Infineon/device-db) | 4.17.0 |
| [Device Database](https://github.com/Infineon/device-db) | 4.18.0 |

## More information

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<View xmlns="http://cypress.com/xsd/cystudioview_v1">
<PinResourceType value="ioss[0].port[%1$d].pin[%2$d]" />
<Profiles>
<Profile displayName="Solutions" fileName="solutions" evalPriority="7" displayPriority="1" description="Solution configuration" resources="vres(\[\d+\]).*" />
<Profile displayName="Connectivity" fileName="connectivity_wifi" evalPriority="1" displayPriority="6" description="Connectivity Wi-Fi configuration" resources="(wifi)(\[\d+\])?\..+" />
<Profile displayName="Connectivity" fileName="connectivity_bt" evalPriority="1" displayPriority="6" description="Connectivity BT configuration" resources="(bt)(\[\d+\])?\..+" />
<Profile displayName="Connectivity" fileName="connectivity_coex" evalPriority="1" displayPriority="6" description="Connectivity Coex configuration" resources="(coex)(\[\d+\])?\..+" />
<Profile displayName="Solutions" fileName="solutions" evalPriority="7" displayPriority="1" description="Solution configuration" resources="vres\[\d+\].*" />
<Profile displayName="Connectivity" fileName="connectivity_wifi" evalPriority="1" displayPriority="6" description="Connectivity Wi-Fi configuration" resources="wifi(\[\d+\])?\..+" />
<Profile displayName="Connectivity" fileName="connectivity_bt" evalPriority="1" displayPriority="6" description="Connectivity BT configuration" resources="bt(\[\d+\])?\..+" />
<Profile displayName="Connectivity" fileName="connectivity_coex" evalPriority="1" displayPriority="6" description="Connectivity Coex configuration" resources="coex(\[\d+\])?\..+" />
<Profile displayName="System" diagramType="CLOCKS" fileName="system" evalPriority="1" displayPriority="5" description="System configuration" resources="srss[\[\.].*" />
<Profile displayName="Pins" diagramType="PACKAGE" fileName="pins" evalPriority="6" displayPriority="3" description="Pin configuration" resources="ioss[\[\.].*" />
<Profile displayName="Peripherals" fileName="peripherals" evalPriority="5" displayPriority="2" description="Peripheral Hardware Block configuration" resources=".*" />
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<View xmlns="http://cypress.com/xsd/cystudioview_v1">
<PinResourceType value="ioss[0].port[%1$d].pin[%2$d]" />
<Profiles>
<Profile displayName="Solutions" fileName="solutions" evalPriority="7" displayPriority="1" description="Solution configuration" resources="vres(\[\d+\]).*" />
<Profile displayName="Connectivity" fileName="connectivity_wifi" evalPriority="1" displayPriority="6" description="Connectivity Wi-Fi configuration" resources="(wifi)(\[\d+\])?\..+" />
<Profile displayName="Connectivity" fileName="connectivity_bt" evalPriority="1" displayPriority="6" description="Connectivity BT configuration" resources="(bt)(\[\d+\])?\..+" />
<Profile displayName="Connectivity" fileName="connectivity_coex" evalPriority="1" displayPriority="6" description="Connectivity Coex configuration" resources="(coex)(\[\d+\])?\..+" />
<Profile displayName="Solutions" fileName="solutions" evalPriority="7" displayPriority="1" description="Solution configuration" resources="vres\[\d+\].*" />
<Profile displayName="Connectivity" fileName="connectivity_wifi" evalPriority="1" displayPriority="6" description="Connectivity Wi-Fi configuration" resources="wifi(\[\d+\])?\..+" />
<Profile displayName="Connectivity" fileName="connectivity_bt" evalPriority="1" displayPriority="6" description="Connectivity BT configuration" resources="bt(\[\d+\])?\..+" />
<Profile displayName="Connectivity" fileName="connectivity_coex" evalPriority="1" displayPriority="6" description="Connectivity Coex configuration" resources="coex(\[\d+\])?\..+" />
<Profile displayName="System" diagramType="CLOCKS" fileName="system" evalPriority="1" displayPriority="5" description="System configuration" resources="srss[\[\.].*" />
<Profile displayName="Pins" diagramType="PACKAGE" fileName="pins" evalPriority="6" displayPriority="4" description="Pin configuration" resources="ioss[\[\.].*" />
<Profile displayName="Power" fileName="peripherals" evalPriority="1" displayPriority="3" description="Power configuration" resources="(power)(\[\d+\])?($|\..+)" />
<Profile displayName="Power" fileName="peripherals" evalPriority="1" displayPriority="3" description="Power configuration" resources="power(\[\d+\])?($|\..+)" />
<Profile displayName="Peripherals" fileName="peripherals" evalPriority="5" displayPriority="2" description="Peripheral Hardware Block configuration" resources=".*" />
<!--This won't match any HW locations because it is after the catchall (.*). This is on purpose and needed to specify display order/code gen order for Analog/routing.-->
<Profile purpose="ROUTING" displayName="Analog-Routing" diagramType="ANALOG" fileName="routing" evalPriority="4" displayPriority="2" description="Establishes all necessary connections between hardware elements." resources="NONE" >
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<!--There are no TriggerGroup type="ONE_TO_ONE" in triggers.cydata so TrigMuxSelectTemplate is not used.-->
<TrigMuxSelectTemplate value="/* NOT USED */" />
<Profiles>
<Profile displayName="Solutions" fileName="solutions" evalPriority="7" displayPriority="1" description="Solution configuration" resources="vres(\[\d+\]).*" />
<Profile displayName="Connectivity" fileName="connectivity_wifi" evalPriority="1" displayPriority="4" description="Connectivity Wi-Fi configuration" resources="(wifi)(\[\d+\])?\..+" />
<Profile displayName="Connectivity" fileName="connectivity_bt" evalPriority="1" displayPriority="4" description="Connectivity BT configuration" resources="(bt)(\[\d+\])?\..+" />
<Profile displayName="Connectivity" fileName="connectivity_coex" evalPriority="1" displayPriority="4" description="Connectivity Coex configuration" resources="(coex)(\[\d+\])?\..+" />
<Profile purpose="MEMORY" displayName="Memory" fileName="memory" evalPriority="8" displayPriority="5" description="Memory configuration" resources="(vres\[\d+\]\.(reserved_memory_region|memory|security)\[\d+\].*)|(m33syscpuss\[\d+\]\.cm33.*)|(m55appcpuss\[\d+\]\.cm55.*)|(.*\.mpc\[\d+\])" />
<Profile displayName="Solutions" fileName="solutions" evalPriority="7" displayPriority="1" description="Solution configuration" resources="vres\[\d+\].*" />
<Profile displayName="Connectivity" fileName="connectivity_wifi" evalPriority="1" displayPriority="4" description="Connectivity Wi-Fi configuration" resources="wifi(\[\d+\])?\..+" />
<Profile displayName="Connectivity" fileName="connectivity_bt" evalPriority="1" displayPriority="4" description="Connectivity BT configuration" resources="bt(\[\d+\])?\..+" />
<Profile displayName="Connectivity" fileName="connectivity_coex" evalPriority="1" displayPriority="4" description="Connectivity Coex configuration" resources="coex(\[\d+\])?\..+" />
<Profile displayName="Pins" diagramType="PACKAGE" fileName="pins" evalPriority="6" displayPriority="2" description="Pin configuration" resources=".*" />
<!--This won't match any HW locations because it is after the catchall (.*). This is on purpose and needed to specify code gen order for routing.-->
<Profile purpose="ROUTING" displayName="" fileName="routing" evalPriority="4" displayPriority="3" description="Establishes all necessary connections between hardware elements." resources="NONE" >
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@@ -1,5 +1,17 @@
<?xml version="1.0" encoding="utf-8"?>
<Woundings xml_version="1" xmlns="http://cypress.com/xsd/cychipresourcewoundings_v1">
<MemoryWounding name="SRAM_KB" memoryId="SRAM"/>

<MemoryWounding name="FLASH_KB" memoryId="FLASH"/>
<!--<MemoryWounding name="FLASH_KB" memoryId="FLASH_LG_SBM"/>-->
<!--<MemoryWounding name="FLASH_KB" memoryId="FLASH_SM_SBM"/>-->
<!--<MemoryWounding name="FLASH_KB" memoryId="FLASH_LG_DBM1"/>-->
<!--<MemoryWounding name="FLASH_KB" memoryId="FLASH_SM_DBM1"/>-->
<!--<MemoryWounding name="WFLASH_KB" memoryId="WFLASH_LG_SBM"/>-->
<!--<MemoryWounding name="WFLASH_KB" memoryId="WFLASH_SM_SBM"/>-->
<!--<MemoryWounding name="WFLASH_KB" memoryId="WFLASH_LG_DBM1"/>-->
<!--<MemoryWounding name="WFLASH_KB" memoryId="WFLASH_SM_DBM1"/>-->

<BooleanWounding name="ECO">
<Block name="srss.clock.eco"/>
</BooleanWounding>
Expand Down Expand Up @@ -92,6 +104,9 @@
<RemoveListWounding name="SMIF_REMOVED">
<Block name="smif.core" />
</RemoveListWounding>
<RemoveListWounding name="I2S_REMOVED">
<Block name="tdm" />
</RemoveListWounding>

<IndexResourceWounding name="I2S_REMOVED">
<ResourceIndex index="0">
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3 changes: 2 additions & 1 deletion device-info/device-db-supplemental/MXS40/studio_5.0/view.xml
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Expand Up @@ -14,7 +14,8 @@
<TrigMuxConnectTemplate value="Cy_TrigMux_Connect(${CyMarkIn}, ${CyMarkOut}, false, ${CyMarkType});" />
<TrigMuxSelectTemplate value="Cy_TrigMux_Select(${CyMarkOut}, false, ${CyMarkType});" />
<Profiles>
<Profile displayName="Solutions" fileName="solutions" evalPriority="7" displayPriority="1" description="Solution configuration" resources="vres(\[\d+\]).*" />
<Profile purpose="MEMORY" displayName="Memory" fileName="memory" evalPriority="8" displayPriority="6" description="Memory configuration" resources="(vres\[\d+\]\.(reserved_memory_region|memory|security)\[\d+\].*)|(m33syscpuss\[\d+\]\.cm33.*)|(m55appcpuss\[\d+\]\.cm55.*)|(.*\.mpc\[\d+\])" />
<Profile displayName="Solutions" fileName="solutions" evalPriority="7" displayPriority="1" description="Solution configuration" resources="vres\[\d+\].*" />
<Profile displayName="System" diagramType="CLOCKS" fileName="system" evalPriority="1" displayPriority="5" description="System configuration" resources="srss(\[\d+\])?\.(clock|power|eeprom)(\[\d+\])?.*|cpuss(\[\d+\])?\.dap(\[\d+\])?" />
<Profile displayName="DMA" fileName="dmas" evalPriority="3" displayPriority="7" description="DMA configuration" resources="cpuss(\[\d+\])?\.(dw|dmac).*|axi_dmac(\[\d+\])?.*" />
<Profile displayName="Peripheral-Clocks" fileName="clocks" evalPriority="2" displayPriority="6" description="Clock configuration" resources="peri(\[\d+\])?(\.group(\[\d+\])?)?(\.div_.*)?" />
Expand Down
5 changes: 5 additions & 0 deletions device-info/device-db-supplemental/MXS40Sv2/CYW20829/info.xml
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@@ -0,0 +1,5 @@
<?xml version="1.0" encoding="utf-8"?>
<info>
<name>CYW20829</name>
<description>The CYW20829 devices</description>
</info>
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@@ -0,0 +1,22 @@
<?xml version="1.0" encoding="utf-8"?>
<View xmlns="http://cypress.com/xsd/cystudioview_v1">
<Profiles>
<Profile purpose="MEMORY" displayName="Memory" fileName="memory" evalPriority="8" displayPriority="6" description="Memory configuration" resources="(vres\[\d+\]\.(reserved_memory_region|memory|security)\[\d+\].*)|(m33syscpuss\[\d+\]\.cm33.*)|(m55appcpuss\[\d+\]\.cm55.*)|(.*\.mpc\[\d+\])" />
<Profile displayName="Solutions" fileName="solutions" evalPriority="7" displayPriority="1" description="Solution configuration" resources="vres\[\d+\].*" />
<Profile displayName="System" diagramType="CLOCKS" fileName="system" evalPriority="1" displayPriority="5" description="System configuration" resources="srss(\[\d+\])?\.(clock|power|eeprom)(\[\d+\])?.*|cpuss(\[\d+\])?\.dap(\[\d+\])?|cpuss(\[\d+\])?\.systick.*" />
<!-- debug600 needs to be shown in System tab, but the code needs to be called from init_cycfg_peripherals. See Jira PLATLIBS-3172 -->
<Profile displayName="System" diagramType="CLOCKS" fileName="peripherals" evalPriority="5" displayPriority="5" description="System configuration" resources="debug600(\[\d+\])?" />
<Profile displayName="DMA" fileName="dmas" evalPriority="3" displayPriority="8" description="DMA configuration" resources="(cpuss|m33syscpuss)(\[\d+\])?\.(dw|dmac|mxdw|mxahbdmac).*" />
<Profile displayName="Peripheral-Clocks" fileName="clocks" evalPriority="2" displayPriority="7" description="Clock configuration" resources="peri(\[\d+\])?\.group(\[\d+\])?(\.div_.*)?" />
<Profile displayName="Pins" diagramType="PACKAGE" fileName="pins" evalPriority="6" displayPriority="3" description="Pin configuration" resources="ioss[\[\.].*" />
<Profile displayName="Peripherals" fileName="peripherals" evalPriority="5" displayPriority="2" description="Peripheral Hardware Block configuration" resources=".*" />
<!--This won't match any HW locations because it is after the catchall (.*). This is on purpose and needed to specify display order/code gen order for Analog/routing.-->
<Profile purpose="ROUTING" displayName="Analog-Routing" diagramType="ANALOG" fileName="routing" evalPriority="4" displayPriority="4" description="Establishes all necessary connections between hardware elements." resources="NONE" >
<Includes>
<Include value="cy_trigmux.h" public="false" />
<Include value="stdbool.h" public="false" />
<Include value="cy_device_headers.h" public="false" />
</Includes>
</Profile>
</Profiles>
</View>
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@@ -1,5 +1,8 @@
<?xml version="1.0" encoding="utf-8"?>
<Woundings xml_version="1" xmlns="http://cypress.com/xsd/cychipresourcewoundings_v1">
<MemoryWounding name="SRAM_KB" memoryId="SRAM"/>
<MemoryWounding name="FLASH_KB" memoryId="FLASH"/>

<BooleanWounding name="SMIF">
<Block name="smif"/>
</BooleanWounding>
Expand All @@ -23,6 +26,9 @@
<BooleanWounding name="MOTIF">
<Block name="tcpwm.group.motif"/>
</BooleanWounding>
<BooleanWounding name="HRPWM">
<Block name="tcpwm.group.cnt.hrpwm"/>
</BooleanWounding>

<NaWounding name="BLUETOOTH">
<Block name="btss"/>
Expand All @@ -46,11 +52,13 @@
</RemoveListWounding>
<RemoveListWounding name="ADC_REMOVED">
<Block name="adcmic"/>
<Block name="pass.sar"/>
</RemoveListWounding>
<RemoveListWounding name="I2S_REMOVED">
<Block name="tdm"/>
</RemoveListWounding>
<RemoveListWounding name="ADC_CH_REMOVED">
<Block name="pass.sar.ch"/>
<Block name="pass.sar.dir_sampler"/>
</RemoveListWounding>
</Woundings>
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17 changes: 0 additions & 17 deletions device-info/device-db-supplemental/MXS40Sv2/studio_5.0/view.xml
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Expand Up @@ -13,21 +13,4 @@
<PinResourceType value="ioss[0].port[%1$d].pin[%2$d]" />
<TrigMuxConnectTemplate value="Cy_TrigMux_Connect(${CyMarkIn}, ${CyMarkOut}, false, ${CyMarkType});" />
<TrigMuxSelectTemplate value="Cy_TrigMux_Select(${CyMarkOut}, false, ${CyMarkType});" />
<Profiles>
<Profile displayName="Solutions" fileName="solutions" evalPriority="7" displayPriority="1" description="Solution configuration" resources="vres(\[\d+\]).*" />
<Profile displayName="System" diagramType="CLOCKS" fileName="system" evalPriority="1" displayPriority="5" description="System configuration" resources="srss(\[\d+\])?\.(clock|power)(\[\d+\])?.*|cpuss(\[\d+\])?\.dap(\[\d+\])?|cpuss(\[\d+\])?\.systick.*" />
<Profile displayName="DMA" fileName="dmas" evalPriority="3" displayPriority="7" description="DMA configuration" resources="(cpuss|m33syscpuss)(\[\d+\])?\.(dw|dmac|mxdw|mxahbdmac).*" />
<Profile displayName="Peripheral-Clocks" fileName="clocks" evalPriority="2" displayPriority="6" description="Clock configuration" resources="peri(\[\d+\])?\.group(\[\d+\])?(\.div_.*)?" />
<Profile displayName="Pins" diagramType="PACKAGE" fileName="pins" evalPriority="6" displayPriority="3" description="Pin configuration" resources="ioss[\[\.].*" />
<Profile displayName="Analog" fileName="analog" evalPriority="4" displayPriority="4" description="HCPASS Configuration" resources="pass\b.*"/>
<Profile displayName="Peripherals" fileName="peripherals" evalPriority="5" displayPriority="2" description="Peripheral Hardware Block configuration" resources=".*" />
<!--This won't match any HW locations because it is after the catchall (.*). This is on purpose and needed to specify display order/code gen order for Analog/routing.-->
<Profile purpose="ROUTING" displayName="Analog-Routing" diagramType="ANALOG" fileName="routing" evalPriority="4" displayPriority="4" description="Establishes all necessary connections between hardware elements." resources="NONE" >
<Includes>
<Include value="cy_trigmux.h" public="false" />
<Include value="stdbool.h" public="false" />
<Include value="cy_device_headers.h" public="false" />
</Includes>
</Profile>
</Profiles>
</View>
2 changes: 1 addition & 1 deletion device-info/device-db-supplemental/version.xml
Original file line number Diff line number Diff line change
@@ -1 +1 @@
<version>4.17.0.6514</version>
<version>4.18.0.7028</version>
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