v0.2: Functional on FPGA

This release marks the design reaching sufficient maturity to run Nexus on an FPGA, meeting timing at 200 MHz on a Xilinx Artix-7 200T. The basic multilayer_8bit design was seen to operate correctly over many thousands of clock cycles, running at ~45 kHz. This simulated clock speed is far below what is expected (~1 MHz), and quite likely limited by inefficient use of the PCIe link to the host.

• RTL updates:
  • New node I/O handling scheme;
  • Mesh traffic regulated through rotating tokens;
  • Refactoring and re-pipelining of many blocks to ease timing;
  • Adding a wrapper layer of hierarchy to convert to/from AXI4-Stream to interface with Xilinx PCIe DMA;
  • Lint issues have been resolved.
• Tool updates:
  • nxcompile updated to work with new node I/O handling scheme;
  • nxmodel updated to work with new compiler output.
• Flow updates:
  • Verilator lint has been integrated as a single make lint within the hardware folder;
  • Out-of-context synthesis of Nexus with both Yosys and Vivado targeting 7-series logic supported using make syn_yosys or make syn_vivado within the hardware folder;
  • Support for running regressions of all testbenches using make regress within the hardware folder.