InvincibleJuggernaut / Synthesis Public

Notifications You must be signed in to change notification settings
Fork 0
Star 0

A collection of digital circuits using Verilog.

0 stars 0 forks Branches Tags Activity

Notifications

Name		Name	Last commit message	Last commit date
Latest commit History 26 Commits
Adders		Adders
Basic Logic Gates		Basic Logic Gates
Encoders/4_2_encoder		Encoders/4_2_encoder
Magnitude Comparator		Magnitude Comparator
Multiplexers		Multiplexers
Multipliers/Multiplier_4		Multipliers/Multiplier_4
README.md		README.md

Repository files navigation

Synthesis

Introduction

This is a collection of digital circuits written in Verilog.

About

A collection of digital circuits using Verilog.

verilog logic-gates digital-circuits verilog-components verilog-programs

Report repository

Releases

No releases published

Packages

No packages published

Languages