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Remove ADDSCR_CLK delayed #9

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JonathSpirit opened this issue Feb 13, 2021 · 0 comments
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Remove ADDSCR_CLK delayed #9

JonathSpirit opened this issue Feb 13, 2021 · 0 comments
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@JonathSpirit
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with JonathSpirit/GP8B#3
there is no need to do that anymore.

@JonathSpirit JonathSpirit added bug Something isn't working medium impact todo labels Feb 13, 2021
@JonathSpirit JonathSpirit self-assigned this Feb 13, 2021
JonathSpirit added a commit that referenced this issue Feb 16, 2021
@JonathSpirit JonathSpirit reopened this Apr 15, 2021
JonathSpirit added a commit that referenced this issue Oct 13, 2021
* Remove compatibility for 5.0, 4.x and add 5.1+

* Fix switched pins on SN74LV393A #7

* Removed capacitor on 12V #11

* Add/Modify power decoupling capacitor #10

* Removing ADDSCR_CLK delay #9

* Schematics : set version 5.1, 2021 copyright and publish date

* Put non-electrolytic capacitor #10

* Set every capacitor size to 0805

* Add new footprint for J7 TE_3-641124-6 #6

* Schematic : set pinHeader on J12 #4

* Netlist, apply change to board, clean track, #6 #4 #12 #10

* Set version to 5.1, 2021 copyright and date, replace the missing QRcode

* Back the MM1 connectors #8

* Replace capacitor for U22 U23 U24 #13

* Better decoupling

* Increase version, year to 2021, clear status

* Precise the molex connector for power supply

* First step, import ses

* Clean bottom layer

* #14 Set the BWRITE2 bus instead of BWRITE1 on U12

* netlist, redo autorouting and cleaning

* use shields.io for colored badge

* Update gerbert files

* Changelog, updated BOM

* Small revision on blockDiagram

* Update README.md

* exporting pcb in pdf

* 3D images, diagram.png

* Update schematics pdf

* redo wavedrom_24bitsCounter
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