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Southern University of Science and Technology
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Digital-Piano
Digital-Piano PublicForked from Layheng-Hok/Digital-Piano
Digital Piano: FPGA project in Verilog based on Xilinx Atrix-7 EGO1 - SUSTech's project of course CS207: Digital Logic in Fall 2023 - Score: 120/100
Verilog
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RISC-V-CPU
RISC-V-CPU PublicForked from Layheng-Hok/RISC-V-CPU
RISC-V CPU: Single-Cycle Processor for RISC-V ISA Built in Verilog - SUSTech's project of course CS202: Computer Organization in Spring 2024 - Score: 104.5/100
VHDL
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Shenzhen-Metro
Shenzhen-Metro PublicForked from Layheng-Hok/Shenzhen-Metro
Shenzhen Metro: Metro Management System - Database and API Design Projects - SUSTech's projects of course CS307: Principles of Database System in Spring 2024 - Scores: 95/100 for Project 1 and 102/…
Java
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