Add new aarch64 cpus

[IanButterworth]

Adds cpu info for:

• arm_cortex_a76
• arm_neoverse_n1: i.e. Amazon AWS Graviton2
• nvidia_carmel: i.e. Nvidia jetson nx

Edit: There seems to be more work needed. With this PR on a Graviton2 machine I get unknown

julia> versioninfo()
Julia Version 1.6.0-DEV.314
Commit a1e2cdebb2 (2020-06-28 18:24 UTC)
Platform Info:
  OS: Linux (aarch64-linux-gnu)
  CPU: unknown
  WORD_SIZE: 64
  LIBM: libopenlibm
  LLVM: libLLVM-9.0.1 (ORCJIT, generic)
Environment:
  JULIA_NUM_THREADS = 16

[yuyichao]

I'll push to this branch for update.

[IanButterworth]

Given neoverse_n1 was added in LLVM 10, I just tried these changes in conjunction with the the LLVM 10 PR on a Graviton2 machine, but still got unknown

julia> versioninfo()
Julia Version 1.6.0-DEV.313
Commit c9ceb36684 (2020-06-28 20:52 UTC)
Platform Info:
  OS: Linux (aarch64-linux-gnu)
  CPU: unknown
  WORD_SIZE: 64
  LIBM: libopenlibm
  LLVM: libLLVM-10.0.0 (ORCJIT, generic)
Environment:
  JULIA_NUM_THREADS = 16

[yuyichao]

There are lot more to change so I squashed down to a single commit. It is possible to split it into a few different commits but it'll mainly be separated by the part of the code they touch rather than by each CPU/feature which is what was there previously.

Unfortunately I still don't have a working aarch64 environment so I can't garantee the code even compile.

CPU: unknown

This is from libuv. Don't expect it to be too smart....

LLVM: libLLVM-10.0.0 (ORCJIT, generic)

This should work though...

[yuyichao]

And in the off chance someone want to backport this. This assumes LLVM >= 8.

[yuyichao]

If the LLVM line is still bad, please post your /proc/cpuinfo, what you get by running ccall(:jl_dump_host_cpu, Cvoid, ()) in julia and what's the content of the /sys/devices/system/cpu/cpu*/regs/identification/midr_el1 files if they exist.

It'll also be helpful for future reference if you could run the program at
https://www.kernel.org/doc/html/latest/arm64/cpu-feature-registers.html#appendix-i-example and paste the output on graveton2.

[IanButterworth]

It's great to be so exhaustive here. Thanks!

On a Graviton2 system from the official 1.4.2 binary:

cat /proc/cpuinfo

$ cat /proc/cpuinfo
processor	: 0
BogoMIPS	: 243.75
Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp ssbs
CPU implementer	: 0x41
CPU architecture: 8
CPU variant	: 0x3
CPU part	: 0xd0c
CPU revision	: 1

processor	: 1
BogoMIPS	: 243.75
Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp ssbs
CPU implementer	: 0x41
CPU architecture: 8
CPU variant	: 0x3
CPU part	: 0xd0c
CPU revision	: 1

processor	: 2
BogoMIPS	: 243.75
Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp ssbs
CPU implementer	: 0x41
CPU architecture: 8
CPU variant	: 0x3
CPU part	: 0xd0c
CPU revision	: 1

processor	: 3
BogoMIPS	: 243.75
Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp ssbs
CPU implementer	: 0x41
CPU architecture: 8
CPU variant	: 0x3
CPU part	: 0xd0c
CPU revision	: 1

processor	: 4
BogoMIPS	: 243.75
Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp ssbs
CPU implementer	: 0x41
CPU architecture: 8
CPU variant	: 0x3
CPU part	: 0xd0c
CPU revision	: 1

processor	: 5
BogoMIPS	: 243.75
Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp ssbs
CPU implementer	: 0x41
CPU architecture: 8
CPU variant	: 0x3
CPU part	: 0xd0c
CPU revision	: 1

processor	: 6
BogoMIPS	: 243.75
Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp ssbs
CPU implementer	: 0x41
CPU architecture: 8
CPU variant	: 0x3
CPU part	: 0xd0c
CPU revision	: 1

processor	: 7
BogoMIPS	: 243.75
Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp ssbs
CPU implementer	: 0x41
CPU architecture: 8
CPU variant	: 0x3
CPU part	: 0xd0c
CPU revision	: 1

processor	: 8
BogoMIPS	: 243.75
Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp ssbs
CPU implementer	: 0x41
CPU architecture: 8
CPU variant	: 0x3
CPU part	: 0xd0c
CPU revision	: 1

processor	: 9
BogoMIPS	: 243.75
Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp ssbs
CPU implementer	: 0x41
CPU architecture: 8
CPU variant	: 0x3
CPU part	: 0xd0c
CPU revision	: 1

processor	: 10
BogoMIPS	: 243.75
Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp ssbs
CPU implementer	: 0x41
CPU architecture: 8
CPU variant	: 0x3
CPU part	: 0xd0c
CPU revision	: 1

processor	: 11
BogoMIPS	: 243.75
Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp ssbs
CPU implementer	: 0x41
CPU architecture: 8
CPU variant	: 0x3
CPU part	: 0xd0c
CPU revision	: 1

processor	: 12
BogoMIPS	: 243.75
Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp ssbs
CPU implementer	: 0x41
CPU architecture: 8
CPU variant	: 0x3
CPU part	: 0xd0c
CPU revision	: 1

processor	: 13
BogoMIPS	: 243.75
Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp ssbs
CPU implementer	: 0x41
CPU architecture: 8
CPU variant	: 0x3
CPU part	: 0xd0c
CPU revision	: 1

processor	: 14
BogoMIPS	: 243.75
Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp ssbs
CPU implementer	: 0x41
CPU architecture: 8
CPU variant	: 0x3
CPU part	: 0xd0c
CPU revision	: 1

processor	: 15
BogoMIPS	: 243.75
Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp ssbs
CPU implementer	: 0x41
CPU architecture: 8
CPU variant	: 0x3
CPU part	: 0xd0c
CPU revision	: 1

julia> ccall(:jl_dump_host_cpu, Cvoid, ())
CPU: generic
Features: crypto, crc, lse, fullfp16, rdm, rcpc, dcpop

cat /sys/devices/system/cpu/cpu0/regs/identification/midr_el1
0x00000000413fd0c1

I checked a random selection through cpu0-15 and they all seem to be the same

I'll retry with this PR ontop of the LLVM 10 PR

[yuyichao]

Can you also try the C program here https://www.kernel.org/doc/html/latest/arm64/cpu-feature-registers.html#appendix-i-example ? It could be useful for some feature detection...

ccall(:jl_dump_host_cpu, Cvoid, ()) on this PR should give you the right name, as is the LLVM version line in versioninfo.

[IanButterworth]

./mrsemu
ID_AA64ISAR0_EL1    : 0x0000100010211120
ID_AA64ISAR1_EL1    : 0x0000000000100001
ID_AA64MMFR0_EL1    : 0x00000000ff000000
ID_AA64MMFR1_EL1    : 0x0000000000000000
ID_AA64PFR0_EL1     : 0x0000000000110011
ID_AA64PFR1_EL1     : 0x0000000000000020
ID_AA64DFR0_EL1     : 0x0000000000000006
ID_AA64DFR1_EL1     : 0x0000000000000000
MIDR_EL1            : 0x00000000413fd0c1
MPIDR_EL1           : 0x0000000080000000
REVIDR_EL1          : 0x0000000000000000

[IanButterworth]

@yuyichao I'm afraid I don't know what happened here.. I didn't merge this PR but it seems a force push I did on my julia fork messed things up and the PR is now considered merged (?!).
I have the files you modified backed up, so I can revert what happened, or if you prefer to, go ahead

[yuyichao]

With the PR closed I don't think I can push to your branch anymore. I've created my branch at https://github.com/JuliaLang/julia/tree/yyc/arm/cpu . If you can't fix this PR I can open one from there.

[IanButterworth]

I've fixed the branch of this PR, but the PR seems to retain the closed state https://github.com/ianshmean/julia/commits/ib/add_aarch64_cpus

It seems I accidentally force-pushed a blank branch due to in-equal states between my local git client and git cli. Github thought it was merged due to being equal to master, but now it's not equal it's not being reopened.

Seems this requires a new PR. I'll open one shortly

Sorry for the mixup