- CMOS Inverter
A CMOS inverter is a type of digital circuit that converts a digital input signal from one state (e.g., 0 or 1) to its opposite state (e.g., 1 or 0). It is a fundamental component of digital electronics that is widely used in digital systems such as microprocessors, digital logic circuits, and digital-to-analog converters.
A CMOS inverter is typically made up of two complementary transistors, one p-type (pMOS) and one n-type (nMOS). The pMOS transistor pulls the output high, while the nMOS transistor pulls the output low. When the inverter's input is high (1), the nMOS transistor is turned on and the pMOS transistor is turned off, resulting in a low output. When the inverter's input is low (0), the pMOS transistor is turned on and the nMOS transistor is turned off, resulting in a high output.
One of the primary advantages of CMOS inverters is their low power consumption, as the transistors are only turned on when the input changes state, rather than constantly drawing current. Moreover, CMOS inverters are highly scalable and easily integrated into larger circuits, making them a popular choice for digital system design.
The schematic circuit is created by connecting components from the open_pdk library.
DC analysis would be used to create a Voltage Transfer Characteristics (VTC) curve for the circuit. It will sweep the value of Vin from high to low to determine how the circuit works with respect to different voltage levels in the input. When the simulation is run, the plot shown below is obtained.
Transient analysis of a circuit is the simulation of the circuit's electrical behaviour over time, specifically its response to changing input signals.
The schematic circuit is created by connecting components from the open_pdk library and performing transient analysis.
** sch_path: /home/venkat/pd/Lab1/inverter_schematic.sch
**.subckt inverter_schematic vout vin vin
*.opin vout
*.ipin vin
*.ipin vin
XM2 vout vin Gnd Gnd sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
XM11 vout vin Vdd Vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
Vdd VDD Gnd 1.8
.save i(vdd)
vin vin Gnd pulse(0 1.8 0 500ps 500ps 4ns 10ns)
.save i(vin)
**** begin user architecture code
** opencircuitdesign pdks install
.lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
.tran 0.01n 50n
.save all
**** end user architecture code
**.ends
.GLOBAL Gnd
.GLOBAL Vdd
.GLOBAL VDD
.end
Copy sky130A.tech and .magicrc to your current working directory and launch the magic using command
magic -T sky130A.tech
Import your inverter's spice netlist into the Layout window
Rearrange the nfet and pfet by pressing i for select and m for moving it to the desired location and add labels/ports. Route the metal1 layer In tkcon window tpye paint m1 in such a way that the layout has no DRC
To extract the spice netlist from the layout, use commands
extract do local
extract all
ext2spice lvs
ext2spice cthresh 0 rthresh 0
ext2spice
* NGSPICE file created from inverter_schematic.ext - technology: sky130A
.subckt sky130_fd_pr__nfet_01v8_648S5X a_n73_n100# a_n33_n188# a_15_n100# a_n175_n274#
X0 a_15_n100# a_n33_n188# a_n73_n100# a_n175_n274# sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
C0 a_n73_n100# a_15_n100# 0.16fF
C1 a_n33_n188# a_n73_n100# 0.03fF
C2 a_n33_n188# a_15_n100# 0.03fF
C3 a_15_n100# a_n175_n274# 0.08fF
C4 a_n73_n100# a_n175_n274# 0.11fF
C5 a_n33_n188# a_n175_n274# 0.30fF
.ends
.subckt sky130_fd_pr__pfet_01v8_XGS3BL a_n73_n100# a_15_n100# w_n211_n319# a_n33_n197#
+ VSUBS
X0 a_15_n100# a_n33_n197# a_n73_n100# w_n211_n319# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
C0 w_n211_n319# a_15_n100# 0.06fF
C1 a_n33_n197# a_n73_n100# 0.03fF
C2 a_n33_n197# a_15_n100# 0.03fF
C3 a_n73_n100# a_15_n100# 0.16fF
C4 w_n211_n319# a_n33_n197# 0.26fF
C5 w_n211_n319# a_n73_n100# 0.09fF
C6 a_15_n100# VSUBS 0.02fF
C7 a_n73_n100# VSUBS 0.02fF
C8 a_n33_n197# VSUBS 0.05fF
C9 w_n211_n319# VSUBS 1.07fF
.ends
.subckt inverter_schematic
XXM2 vout vin vout VSUBS sky130_fd_pr__nfet_01v8_648S5X
XXM11 vout vout XM11/w_n211_n319# vin VSUBS sky130_fd_pr__pfet_01v8_XGS3BL
C0 vout XM11/w_n211_n319# 0.24fF
C1 vout vin 0.68fF
C2 vin XM11/w_n211_n319# 0.08fF
C3 vin VSUBS 0.61fF
C4 vout VSUBS 1.41fF
C5 XM11/w_n211_n319# VSUBS 1.10fF
.ends
open the post-layout netlist in ngspice
ngspice inverter_schematic.spice
From the transient response, we will now characterise the cell's slew rate and propagation delay
-
Rise transiton - time taken by output waveform to transit from 20%(0.36v) to 80%(1.44v) of VDD(1.8v max value)
4.83095e-09 - 4.78239e-09 = 0.05ns = 50ps
-
Fall transition - time taken by output waveform to transit from 80% (1.44v) to 20% (0.36v) of VDD
1.02815 - 1.02459 = 0.00356ns = 3.56ps
-
Rise cell delay - The difference between the time when output as well as input is at 50% (0.9v) i.e falling at 50% of output is rising
4.80833 - 4.75208 = 0.05625ns = 56.25ps
-
Fall cell delay - The difference between the time when output as well as input is at 50% (0.9v) i.e falling at 50% of input is rising
1.02651 - 1.025 = 0.00151ns = 1.51ps
Perform an LVS check on the pre-layout and post-layout netlists
netgen -batch lvs /home/venkat/pd/Lab1/inverter_schematic.spice /home/venkat/pd/Lab1/mag/inverter_schematic.spice
