Electronic Design Automation course project is a Python script that generates a Verilog testbench file using the HDLParse library. The generated testbench can be used to simulate the behavior of a digital logic design described in Verilog .
- To use this script, you will need to have Python and the HDLParse library installed on your system.
- Another way to use this script by downloading the executable file and using it directly without any prerequisites.
- Python 3.x
- HDLParse library
- You can install the dependencies by running the following command:
pip install hdlparse
- This script doesn't generate a correct testbench if the verilog code has
clk(may be we implement it soon)
