stm32: h7 spi support reload mode & frequency

Signed-off-by: Timofey Titovets <nefelim4ag@gmail.com>
Klipper3d · Jan 30, 2025 · 79dc0b6 · 79dc0b6
1 parent 0114d72
commit 79dc0b6
Show file tree

Hide file tree

Showing 2 changed files with 18 additions and 3 deletions.
diff --git a/src/stm32/gpio.h b/src/stm32/gpio.h
@@ -38,7 +38,13 @@ void gpio_adc_cancel_sample(struct gpio_adc g);
 
 struct spi_config {
     void *spi;
-    uint32_t spi_cr1;
+    union {
+        uint32_t spi_cr1;
+        struct {
+            uint8_t div;
+            uint8_t mode;
+        };
+    };
 };
 struct spi_config spi_setup(uint32_t bus, uint8_t mode, uint32_t rate);
 void spi_prepare(struct spi_config config);

diff --git a/src/stm32/stm32h7_spi.c b/src/stm32/stm32h7_spi.c
@@ -13,6 +13,7 @@
 struct spi_info {
     SPI_TypeDef *spi;
     uint8_t miso_pin, mosi_pin, sck_pin, function;
+    uint8_t div, mode;
 };
 
 DECL_ENUMERATION("spi_bus", "spi2", __COUNTER__);
@@ -100,19 +101,27 @@ spi_setup(uint32_t bus, uint8_t mode, uint32_t rate)
     while ((pclk >> (div + 1)) > rate && div < 7)
         div++;
 
-    uint32_t cr1 = SPI_CR1_SPE;
     spi->CFG1 |= (div << SPI_CFG1_MBR_Pos) | (7 << SPI_CFG1_DSIZE_Pos);
     CLEAR_BIT(spi->CFG1, SPI_CFG1_CRCSIZE);
     spi->CFG2 |= ((mode << SPI_CFG2_CPHA_Pos) | SPI_CFG2_MASTER | SPI_CFG2_SSM
                    | SPI_CFG2_AFCNTR | SPI_CFG2_SSOE);
     spi->CR1 |= SPI_CR1_SSI;
 
-    return (struct spi_config){ .spi = spi, .spi_cr1 = cr1 };
+    return (struct spi_config){ .spi = spi, .div = div, .mode = mode };
 }
 
 void
 spi_prepare(struct spi_config config)
 {
+    uint32_t div = config.div;
+    uint32_t mode = config.mode;
+    SPI_TypeDef *spi = config.spi;
+    // Reload frequency
+    spi->CFG1 = (spi->CFG1 & ~SPI_CFG1_MBR_Msk);
+    spi->CFG1 |= (div << SPI_CFG1_MBR_Pos);
+    // Reload mode
+    spi->CFG2 = (spi->CFG2 & ~SPI_CFG2_CPHA_Msk);
+    spi->CFG2 |= (mode << SPI_CFG2_CPHA_Pos);
 }
 
 void