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Initialize ARM CPU model ID
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amarathe84 committed Jul 25, 2023
1 parent 5150443 commit 0682a7c
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Showing 2 changed files with 46 additions and 39 deletions.
1 change: 1 addition & 0 deletions src/variorum/AMD_GPU/config_amd_gpu.c
Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,7 @@ int set_amd_gpu_func_ptrs(int idx)
{
static int init_complete = 0;
int err = 0;
rsmi_status_t ret;

if (*g_platform[idx].arch_id == AMD_INSTINCT)
{
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84 changes: 45 additions & 39 deletions src/variorum/ARM/config_arm.c
Original file line number Diff line number Diff line change
Expand Up @@ -25,49 +25,55 @@ uint64_t *detect_arm_arch(void)
uint64_t cpu0_id_val;
uint64_t cpu1_id_val;

/* This logic reads the IDs for the first two cores on the system.
* On the ARM big.LITTLE system, the first two cores report the CPU IDs
* from the big and LITTLE clusters, respectively, on the SoC.
* On the Neoverse N1 system, the first two cores report identical
* CPU IDs. Variorum checks the combined CPU IDs returned by the system.
*/
char *cpu0_id_reg_path =
"/sys/devices/system/cpu/cpu0/regs/identification/midr_el1";
char *cpu1_id_reg_path =
"/sys/devices/system/cpu/cpu1/regs/identification/midr_el1";
unsigned long *model = (unsigned long *) malloc(sizeof(uint64_t));

int cpu0_id_reg_fd = open(cpu0_id_reg_path, O_RDONLY);
int cpu1_id_reg_fd = open(cpu1_id_reg_path, O_RDONLY);

if (!cpu0_id_reg_fd || !cpu1_id_reg_fd)
{
variorum_error_handler("Error encountered in accessing CPU ID information",
VARIORUM_ERROR_INVAL, getenv("HOSTNAME"),
__FILE__, __FUNCTION__, __LINE__);
return NULL;
}
static unsigned long model_id = -1;

int cpu0_id_bytes = read(cpu0_id_reg_fd, cpu0_id_str, CPU_ID_SIZE);
int cpu1_id_bytes = read(cpu1_id_reg_fd, cpu1_id_str, CPU_ID_SIZE);

if (!cpu0_id_bytes || !cpu1_id_bytes)
if (model_id == -1)
{
variorum_error_handler("Error encountered in accessing CPU ID information",
VARIORUM_ERROR_INVAL, getenv("HOSTNAME"),
__FILE__, __FUNCTION__, __LINE__);
return NULL;
/* This logic reads the IDs for the first two cores on the system.
* On the ARM big.LITTLE system, the first two cores report the CPU IDs
* from the big and LITTLE clusters, respectively, on the SoC.
* On the Neoverse N1 system, the first two cores report identical
* CPU IDs. Variorum checks the combined CPU IDs returned by the system.
*/
char *cpu0_id_reg_path =
"/sys/devices/system/cpu/cpu0/regs/identification/midr_el1";
char *cpu1_id_reg_path =
"/sys/devices/system/cpu/cpu1/regs/identification/midr_el1";

int cpu0_id_reg_fd = open(cpu0_id_reg_path, O_RDONLY);
int cpu1_id_reg_fd = open(cpu1_id_reg_path, O_RDONLY);

if (!cpu0_id_reg_fd || !cpu1_id_reg_fd)
{
variorum_error_handler("Error encountered in accessing CPU ID information",
VARIORUM_ERROR_INVAL, getenv("HOSTNAME"),
__FILE__, __FUNCTION__, __LINE__);
return NULL;
}

int cpu0_id_bytes = read(cpu0_id_reg_fd, cpu0_id_str, CPU_ID_SIZE);
int cpu1_id_bytes = read(cpu1_id_reg_fd, cpu1_id_str, CPU_ID_SIZE);

if (!cpu0_id_bytes || !cpu1_id_bytes)
{
variorum_error_handler("Error encountered in accessing CPU ID information",
VARIORUM_ERROR_INVAL, getenv("HOSTNAME"),
__FILE__, __FUNCTION__, __LINE__);
return NULL;
}

cpu0_id_val = strtol(cpu0_id_str, NULL, 16);
cpu1_id_val = strtol(cpu1_id_str, NULL, 16);

model_id = (cpu0_id_val & 0x000000000000fff0) << 8;
model_id |= ((cpu1_id_val & 0x000000000000fff0) >> 4);

close(cpu0_id_reg_fd);
close(cpu1_id_reg_fd);
}

cpu0_id_val = strtol(cpu0_id_str, NULL, 16);
cpu1_id_val = strtol(cpu1_id_str, NULL, 16);

*model = (cpu0_id_val & 0x000000000000fff0) << 8;
*model |= ((cpu1_id_val & 0x000000000000fff0) >> 4);

close(cpu0_id_reg_fd);
close(cpu1_id_reg_fd);

unsigned long *model = (unsigned long *) malloc(sizeof(uint64_t));
*model = model_id;
return model;
}

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