Add PEBS Latency API

src/examples/variorum-print-topology-example.c

@@ -20,14 +20,15 @@ int main(int argc, char **argv)
                 printf(usage, argv[0]);
                 return 0;
             case 'v':
-                printf("%s\n", variorum_get_current_version());
+                variorum_PEBS_print_latency();
                 return 0;
             default:
                 fprintf(stderr, usage, argv[0]);
                 return -1;
         }
     }
 
-    variorum_print_topology();
+    //variorum_print_topology();
+    variorum_PEBS_print_latency();
     return 0;
 }

src/variorum/Intel/Intel_06_2A.c

@@ -31,6 +31,8 @@ static struct sandybridge_2a_offsets msrs =
     .ia32_fixed_counters[0]       = 0x309,
     .ia32_fixed_counters[1]       = 0x30A,
     .ia32_fixed_counters[2]       = 0x30B,
+    .ia32_pebs_enable             = 0x3F1,
+    .msr_pebs_ld_lat              = 0x3F6,
     .ia32_fixed_ctr_ctrl          = 0x38D,
     .ia32_perf_global_status      = 0x38E,
     .ia32_perf_global_ctrl        = 0x38F,
@@ -331,6 +333,7 @@ int intel_cpu_fm_06_2a_get_clocks_json(json_t *get_clock_obj_json)
     return 0;
 }
 
+
 int intel_cpu_fm_06_2a_get_power(int long_ver)
 {
     char *val = getenv("VARIORUM_LOG");

src/variorum/Intel/Intel_06_2A.h

@@ -36,6 +36,10 @@ struct sandybridge_2a_offsets
     off_t ia32_package_therm_status;
     /// @brief Address for IA32_PACKAGE_THERM_INTERRUPT.
     off_t ia32_package_therm_interrupt;
+    /// @brief Address for IA32_PEBS_ENABLE.
+    off_t ia32_pebs_enable;
+    /// @brief Address for MSR_PEBS_LD_LAT.
+    off_t msr_pebs_ld_lat;
     /// @brief Address for IA32_FIXED_CTR_CTRL.
     off_t ia32_fixed_ctr_ctrl;
     /// @brief Address for IA32_PERF_GLOBAL_STATUS.
@@ -86,6 +90,7 @@ int intel_cpu_fm_06_2a_cap_power_limits(
     int package_power_limit
 );
 
+
 int intel_cpu_fm_06_2a_get_features(
     void
 );

src/variorum/Intel/Intel_06_4F.c

@@ -16,6 +16,8 @@
 
 static struct broadwell_4f_offsets msrs =
 {
+    .ia32_pebs_enable             = 0x3F1,
+    .msr_pebs_ld_lat              = 0x3F6,
     .msr_platform_info            = 0xCE,
     .ia32_time_stamp_counter      = 0x10,
     .ia32_perf_ctl                = 0x199,
@@ -73,6 +75,20 @@ static struct broadwell_4f_offsets msrs =
     .msrs_pcu_pmon_evtsel[3]      = 0xC33
 };
 
+int variorum_PEBS_print_l2(void)
+{
+<<<<<<< HEAD
+    unsigned int PEBS_disable_bit = 0;
+    PEBS_laten(msrs.ia32_pebs_enable, PEBS_disable_bit);
+=======
+    unsigned int PEBS_disable_bit = 1;
+    //PEBS_laten(msrs.ia32_pebs_enable, PEBS_disable_bit);
+    printf("IM HERE \n");
+    PEBS_laten(msrs.ia32_mperf, PEBS_disable_bit);
+>>>>>>> c151a0f30eec5787676c7db1a978b43228d44ab5
+    return 0;
+}
+
 int intel_cpu_fm_06_4f_get_power_limits(int long_ver)
 {
     unsigned socket;

src/variorum/Intel/Intel_06_4F.h

@@ -12,6 +12,10 @@
 /// @brief List of unique addresses for Broadwell Family/Model 4FH.
 struct broadwell_4f_offsets
 {
+    /// @brief Address for IA32_PEBS_ENABLE.
+    off_t ia32_pebs_enable;
+    /// @brief Address for MSR_PEBS_LD_LAT.
+    off_t msr_pebs_ld_lat;
     /// @brief Address for MSR_PLATFORM_INFO.
     off_t msr_platform_info;
     /// @brief Address for IA32_TIME_STAMP_COUNTER.
@@ -83,6 +87,10 @@ struct broadwell_4f_offsets
     off_t msr_config_tdp_nominal;
 };
 
+int variorum_PEBS_print_l2(
+    void
+);
+
 int intel_cpu_fm_06_4f_get_power_limits(
     int long_ver
 );

src/variorum/Intel/config_intel.c

@@ -202,6 +202,7 @@ int set_intel_func_ptrs(int idx)
     // Broadwell 06_4F
     else if (*g_platform[idx].arch_id == FM_06_4F)
     {
+        g_platform[idx].variorum_PEBS_print_latency =  variorum_PEBS_print_l2;
         g_platform[idx].variorum_print_power_limit =
             intel_cpu_fm_06_4f_get_power_limits;
         g_platform[idx].variorum_cap_each_socket_power_limit =

src/variorum/Intel/counters_features.c

@@ -2,14 +2,16 @@
 // Variorum Project Developers. See the top-level LICENSE file for details.
 //
 // SPDX-License-Identifier: MIT
-
+//
+#include <inttypes.h>
+#include <misc_features.h>
+//
 #include <stddef.h>
 #include <stdint.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <sys/time.h>
 #include <unistd.h>
-
 #include <clocks_features.h>
 #include <counters_features.h>
 #include <config_architecture.h>
@@ -42,6 +44,46 @@ int cpuid_num_pmc(void)
 /* Fixed Counters Performance Monitoring */
 /*****************************************/
 
+int PEBS_laten(off_t msr, unsigned int PEBS_disable_bit)
+{
+    //read_msr_by_coord(unsigned socket, unsigned core, unsigned thread, off_t msr, uint64_t *val)
+    //write_msr_by_coord(unsigned socket, unsigned core, unsigned thread, off_t msr, uint64_t val)
+
+    int ret = 0;
+    int ret_two = 0;
+    unsigned socket = 0;
+    unsigned core = 0;
+    unsigned thread = 0;
+    unsigned nsockets;
+    uint64_t mask = 0;
+    uint64_t msr_val = 0;
+
+    //variorum_get_topology(&nsockets, NULL, NULL, P_INTEL_CPU_IDX);
+
+    //mask |= 1LL << PEBS_disable_bit;
+
+    //for (socket = 0; socket < nsockets; socket++)
+    //{
+    //    ret = read_msr_by_coord(socket, core, thread, msr, &msr_val);
+    //    printf("socket, core, thread, msr, msr_loc, msr_val = %d, %d, %d, %lx, %p, (%#"PRIx64")\n", socket, core, thread, msr, &msr_val, msr_val);
+
+ 	//	uint64_t write_val = 1;
+   	//	ret_two = write_msr_by_coord(socket, core, thread, msr, write_val);
+    //	printf("socket, core, thread, msr, write_val = %d, %d, %d, %lx, (%#"PRIx64")\n", socket, core, thread, msr, write_val);
+
+    //}
+
+	read_msr_by_coord(socket, core, thread, msr, &msr_val);
+	printf("msr_val = (%#"PRIx64")\n", msr_val);
+	uint64_t write_val = 1;
+	write_msr_by_coord(socket, core, thread, msr, write_val);
+	printf("write_val = (%#"PRIx64")\n", write_val);	
+    read_batch(PEBS_CONFIG);
+    return 0;
+}
+
+
+
 void fixed_counter_storage(struct fixed_counter **ctr0,
                            struct fixed_counter **ctr1, struct fixed_counter **ctr2,
                            off_t *msrs_fixed_ctrs)
@@ -96,6 +138,31 @@ void init_fixed_counter(struct fixed_counter *ctr)
     ctr->value = (uint64_t **) malloc(nthreads * sizeof(uint64_t *));
 }
 
+static int init_PEBS(struct PEBS *evt, off_t *msrs_pebs)
+{
+    unsigned nthreads;
+    int avail = cpuid_num_pmc();
+    variorum_get_topology(NULL, NULL, &nthreads, P_INTEL_CPU_IDX);
+
+    if (avail < 1)
+    {
+        return -1;
+    }
+    switch (avail)
+    {
+		case 1:
+		evt->perfmon_counters0 = (uint64_t **) calloc(nthreads, sizeof(uint64_t *));
+		evt->perfmon_counters1 = (uint64_t **) calloc(nthreads, sizeof(uint64_t *));
+		evt->perfmon_counters2 = (uint64_t **) calloc(nthreads, sizeof(uint64_t *));
+		evt->perfmon_counters3 = (uint64_t **) calloc(nthreads, sizeof(uint64_t *));
+		evt->perfevtsel_counters0 = (uint64_t **) calloc(nthreads, sizeof(uint64_t *));
+		evt->perfevtsel_counters1 = (uint64_t **) calloc(nthreads, sizeof(uint64_t *));
+		evt->perfevtsel_counters2 = (uint64_t **) calloc(nthreads, sizeof(uint64_t *));
+		evt->perfevtsel_counters3 = (uint64_t **) calloc(nthreads, sizeof(uint64_t *));
+		break;
+    }
+}
+
 void enable_fixed_counters(off_t *msrs_fixed_ctrs, off_t msr1, off_t msr2)
 {
     struct fixed_counter *c0, *c1, *c2;
@@ -619,6 +686,8 @@ void print_verbose_perfmon_counter_data(FILE *writedest,
 ///
 /// @return 0 if successful, else -1 if number of general-purpose performance
 /// counters is less than 1.
+
+
 static int init_pmc(struct pmc *p, off_t *msrs_perfmon_ctrs)
 {
     unsigned nthreads = 0;

src/variorum/Intel/counters_features.h

@@ -35,6 +35,16 @@ struct fixed_counter
     uint64_t *overflow;
 };
 
+struct PEBS_counter
+{
+    uint64_t *enable;
+    uint64_t *ring_level;
+    uint64_t *anyThread;
+    uint64_t *pmi;
+    uint64_t **value;
+    uint64_t *overflow;
+};
+
 /// @brief Structure containing general information about the fixed-function
 /// performance counters on the platform.
 struct fixed_counter_config
@@ -49,7 +59,35 @@ struct fixed_counter_config
 /*****************************************/
 /* Fixed Counters Performance Monitoring */
 /*****************************************/
+int PEBS_laten(
+   off_t msr,
+   unsigned int PEBS_disable_bit 
+);
 
+void PEBS_counter_storage(
+    struct PEBS_counter **ctr0,
+    struct PEBS_counter **ctr1,
+    struct PEBS_counter **ctr2,
+    struct PEBS_counter **ctr3,
+    struct PEBS_counter **perfevtsel0,
+    struct PEBS_counter **perfevtsel1,
+    struct PEBS_counter **perfevtsel2,
+    struct PEBS_counter **perfevtsel3,
+    struct PEBS_counter **perfglobalctrl,
+    struct PEBS_counter **perfglobalstatus,
+    struct PEBS_counter **perfglobalovfctrl,
+    struct PEBS_counter **debugctl,
+    struct PEBS_counter **fixedctrctrl,
+    struct PEBS_counter **pebsenable,
+    struct PEBS_counter **pebsldlatthreshold,
+    struct PEBS_counter **miscenable,
+    struct PEBS_counter **perfcapabilities,
+    struct PEBS_counter **fixedctr0,
+    struct PEBS_counter **fixedctr1,
+    struct PEBS_counter **fixedctr2,
+    struct PEBS_counter **d5area,
+    off_t *msrs_PEBS_ctrs
+);
 /// @brief Initialize storage for fixed-function performance counter data, and
 /// store it on the heap.
 ///
@@ -75,6 +113,11 @@ void init_fixed_counter(
     struct fixed_counter *ctr
 );
 
+static int init_PEBS(
+    struct PEBS *evt,
+    off_t *msrs_pebs
+);
+
 /// @brief Set value of IA32_FIXED_CTR_CTL and IA32_PERF_GLOBAL_CTL and reset
 /// all fixed-function performance counters on all logical processors.
 ///
@@ -284,6 +327,7 @@ int enable_pmc(
 /// @param [in] thread Unique logical processor identifier.
 /// @param [in] msrs_perfevtsel_ctrs Array of unique addresses for
 ///        PERFEVTSEL_CTRS.
+
 void set_pmc_ctrl_flags(
     uint64_t cmask,
     uint64_t flags,

src/variorum/Intel/intel_power_features.c

@@ -771,6 +771,7 @@ int get_dram_rapl_limit(const unsigned socket, struct rapl_limit *limit,
     return 0;
 }
 
+
 int cap_package_power_limit(const unsigned socket, int package_power_limit,
                             off_t msr_power_limit, off_t msr_rapl_unit)
 {

src/variorum/Intel/misc_features.c

@@ -504,7 +504,7 @@ int set_turbo_on(off_t msr_misc_enable, unsigned int turbo_mode_disable_bit)
             return ret;
         }
 
-        /// Does the msr value have the turbo disable bit on?
+        // Does the msr value have the turbo disable bit on?
         if (msr_val == (msr_val | mask))
         {
             uint64_t write_val = msr_val & ~mask;

src/variorum/config_architecture.c

@@ -336,6 +336,7 @@ void variorum_init_func_ptrs()
     int i = 0;
     for (i = 0; i < P_NUM_PLATFORMS; i++)
     {
+        g_platform[i].variorum_PEBS_print_latency = NULL;
         g_platform[i].variorum_print_power_limit = NULL;
         g_platform[i].variorum_cap_socket_frequency_limit = NULL;
         g_platform[i].variorum_cap_best_effort_node_power_limit = NULL;

src/variorum/config_architecture.h

@@ -161,6 +161,15 @@ struct platform
     /// both sockets.
     ///
     /// @return Error code.
+
+
+
+    int (*variorum_PEBS_print_latency)(void); 
+
+
+
+
+
     int (*variorum_cap_gpu_power_ratio)(int gpu_power_ratio);
 
     /// @brief Function pointer to set a power limit to each socket.

src/variorum/msr/msr_core.c

@@ -545,9 +545,15 @@ int read_msr_by_idx(int dev_idx, off_t msr, uint64_t *val)
             getenv("HOSTNAME"), __FILE__, __LINE__, msr, msr);
 #endif
     rc = pread(*file_descriptor, (void *)val, (size_t)sizeof(uint64_t), msr);
+    if (rc == -1)
+    {
+        perror("Error found");
+        printf("file_descriptor = %d\n", *file_descriptor);
+        return 0;
+    }
     if (rc != sizeof(uint64_t))
     {
-        sprintf(variorum_error_msg, "Pread failed on dev_idx %d", dev_idx);
+        sprintf(variorum_error_msg, "Pread failed on dev_idx and rc  %d, %d", dev_idx, rc);
         variorum_error_handler(variorum_error_msg, VARIORUM_ERROR_MSR_READ,
                                getenv("HOSTNAME"), __FILE__, __FUNCTION__, __LINE__);
         free(variorum_error_msg);

src/variorum/msr/msr_core.h

@@ -102,6 +102,7 @@ enum variorum_data_type_e
     TURBO_RATIO_LIMIT_CORES = 34,
     TDP_DEFS = 35,
     TDP_CONFIG = 36,
+    PEBS_CONFIG = 37,
 };
 
 /// @brief Enum encompassing batch operations.