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More strict card name checking broke because names were missing from …
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…list

Also add some new cards
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@pcw-mesa
pcw-mesa committed Nov 4, 2023
1 parent 3217b03 commit c0c803d
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Showing 2 changed files with 90 additions and 0 deletions.
4 changes: 4 additions & 0 deletions anyio.c
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Original file line number Diff line number Diff line change
Expand Up @@ -36,14 +36,18 @@ supported_board_entry_t supported_boards[] = {
{"7I92T", BOARD_ETH},
{"7I93", BOARD_ETH},
{"7I94", BOARD_ETH},
{"7I94T", BOARD_ETH},
{"7I95", BOARD_ETH},
{"7I95T", BOARD_ETH},
{"7I96", BOARD_ETH},
{"7I96S", BOARD_ETH},
{"7I97", BOARD_ETH},
{"7I97T", BOARD_ETH},
{"7I98", BOARD_ETH},
{"7I80", BOARD_ETH},
{"7I80HDT", BOARD_ETH},
{"7I76E", BOARD_ETH},
{"7I76EU", BOARD_ETH},

{"LITEHM2", BOARD_ETH},

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86 changes: 86 additions & 0 deletions eth_boards.c
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Original file line number Diff line number Diff line change
Expand Up @@ -322,6 +322,34 @@ static int eth_scan_one_addr(board_access_t *access) {
board->fallback_support = 1;
board->llio.verbose = access->verbose;
boards_count ++;
} else if (strncmp(buff, "7I76EU", 16) == 0) {
board->type = BOARD_ETH;
board->fpga_type = FPGA_TYPE_EFINIX;
strncpy(board->dev_addr, eth_socket_get_src_ip(), 16);
strncpy(board->llio.board_name, buff, 16);
board->llio.num_ioport_connectors = 3;
board->llio.pins_per_connector = 17;
board->llio.ioport_connector_name[0] = "on-card";
board->llio.ioport_connector_name[1] = "P1";
board->llio.ioport_connector_name[2] = "P2";
board->llio.bob_hint[0] = BOB_7I76;
board->llio.fpga_part_number = "T20F256";
board->llio.num_leds = 4;
board->llio.read = &eth_read;
board->llio.write = &eth_write;
board->llio.write_flash = &remote_write_flash;
board->llio.verify_flash = &remote_verify_flash;
board->llio.backup_flash = &remote_backup_flash;
board->llio.restore_flash = &remote_restore_flash;
board->llio.reset = &lbp16_board_reset;
board->llio.reload = &lbp16_board_reload;
board->open = &eth_board_open;
board->close = &eth_board_close;
board->print_info = &eth_print_info;
board->flash = BOARD_FLASH_REMOTE;
board->fallback_support = 1;
board->llio.verbose = access->verbose;
boards_count ++;
} else if (strncmp(buff, "7I92", 16) == 0) {
board->type = BOARD_ETH;
strncpy(board->dev_addr, eth_socket_get_src_ip(), 16);
Expand Down Expand Up @@ -425,6 +453,34 @@ static int eth_scan_one_addr(board_access_t *access) {
board->fallback_support = 1;
board->llio.verbose = access->verbose;
boards_count ++;
} else if (strncmp(buff, "7I94T", 16) == 0) {
board->type = BOARD_ETH;
board->fpga_type = FPGA_TYPE_EFINIX;
strncpy(board->dev_addr, eth_socket_get_src_ip(), 16);
strncpy(board->llio.board_name, buff, 16);
board->llio.num_ioport_connectors = 2;
board->llio.pins_per_connector = 21;
board->llio.ioport_connector_name[0] = "Expansion+Serial 0..1";
board->llio.ioport_connector_name[1] = "Serial 1..7";
board->llio.bob_hint[0] = BOB_7I94_0;
board->llio.bob_hint[1] = BOB_7I94_1;
board->llio.fpga_part_number = "T20F256";
board->llio.num_leds = 4;
board->llio.read = &eth_read;
board->llio.write = &eth_write;
board->llio.write_flash = &remote_write_flash;
board->llio.verify_flash = &remote_verify_flash;
board->llio.backup_flash = &remote_backup_flash;
board->llio.restore_flash = &remote_restore_flash;
board->llio.reset = &lbp16_board_reset;
board->llio.reload = &lbp16_board_reload;
board->open = &eth_board_open;
board->close = &eth_board_close;
board->print_info = &eth_print_info;
board->flash = BOARD_FLASH_REMOTE;
board->fallback_support = 1;
board->llio.verbose = access->verbose;
boards_count ++;
} else if (strncmp(buff, "7I95", 16) == 0) {
board->type = BOARD_ETH;
strncpy(board->dev_addr, eth_socket_get_src_ip(), 16);
Expand Down Expand Up @@ -568,6 +624,36 @@ static int eth_scan_one_addr(board_access_t *access) {
board->fallback_support = 1;
board->llio.verbose = access->verbose;
boards_count ++;
} else if (strncmp(buff, "7I97T", 16) == 0) {
board->type = BOARD_ETH;
board->fpga_type = FPGA_TYPE_EFINIX;
strncpy(board->dev_addr, eth_socket_get_src_ip(), 16);
strncpy(board->llio.board_name, buff, 16);
board->llio.num_ioport_connectors = 3;
board->llio.pins_per_connector = 17;
board->llio.ioport_connector_name[0] = "TB1/TB2/TB3";
board->llio.ioport_connector_name[1] = "TB4/TB5";
board->llio.ioport_connector_name[2] = "P1";
board->llio.bob_hint[0] = BOB_7I97_0;
board->llio.bob_hint[1] = BOB_7I97_1;
board->llio.bob_hint[2] = BOB_7I97_2;
board->llio.fpga_part_number = "T20F256";
board->llio.num_leds = 4;
board->llio.read = &eth_read;
board->llio.write = &eth_write;
board->llio.write_flash = &remote_write_flash;
board->llio.verify_flash = &remote_verify_flash;
board->llio.backup_flash = &remote_backup_flash;
board->llio.restore_flash = &remote_restore_flash;
board->llio.reset = &lbp16_board_reset;
board->llio.reload = &lbp16_board_reload;
board->open = &eth_board_open;
board->close = &eth_board_close;
board->print_info = &eth_print_info;
board->flash = BOARD_FLASH_REMOTE;
board->fallback_support = 1;
board->llio.verbose = access->verbose;
boards_count ++;
} else if (strncmp(buff, "7I98", 16) == 0) {
board->type = BOARD_ETH;
strncpy(board->dev_addr, eth_socket_get_src_ip(), 16);
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