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  1. HDLGen-ChatGPT HDLGen-ChatGPT Public

    HDLGen-ChatGPT, works in tandem with ChatGPT-3.5 chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and t…

    Python 17 11

  2. PYNQ-SoC-Builder PYNQ-SoC-Builder Public

    This project automates process of creating a PYNQ Z2 Overlay in Vivado, generates a custom Juypter Notebook template and uploads to a target PYNQ FPGA.

    Python 1 2

  3. RISCV-Assembler RISCV-Assembler Public

    RISC-V Assembler in a Jupyter Notebook

    Jupyter Notebook 1

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Showing 3 of 3 repositories
  • PYNQ-SoC-Builder Public

    This project automates process of creating a PYNQ Z2 Overlay in Vivado, generates a custom Juypter Notebook template and uploads to a target PYNQ FPGA.

    Logicademy/PYNQ-SoC-Builder’s past year of commit activity
    Python 1 AGPL-3.0 2 0 0 Updated Sep 21, 2024
  • RISCV-Assembler Public

    RISC-V Assembler in a Jupyter Notebook

    Logicademy/RISCV-Assembler’s past year of commit activity
    Jupyter Notebook 1 0 0 0 Updated Sep 17, 2024
  • HDLGen-ChatGPT Public

    HDLGen-ChatGPT, works in tandem with ChatGPT-3.5 chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) project

    Logicademy/HDLGen-ChatGPT’s past year of commit activity
    Python 17 AGPL-3.0 11 10 (6 issues need help) 0 Updated May 22, 2024

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