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[SOL] Remove LE byte swap and input buffers (anza-xyz#75)
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This PR addressed two more items in solana-labs/solana#34250.
It removes the little endian byte swap instructions (solana-labs/rbpf#493)
and the input buffers related instructions (solana-labs/rbpf#251).
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@LucasSte
LucasSte committed Jun 28, 2024
1 parent 84575f1 commit 1d7960f
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Showing 7 changed files with 24 additions and 129 deletions.
59 changes: 24 additions & 35 deletions llvm/lib/Target/SBF/Disassembler/SBFDisassembler.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -44,12 +44,7 @@ class SBFDisassembler : public MCDisassembler {
SBF_ALU64 = 0x7
};

enum SBF_SIZE {
SBF_W = 0x0,
SBF_H = 0x1,
SBF_B = 0x2,
SBF_DW = 0x3
};
enum SBF_SIZE { SBF_W = 0x0, SBF_H = 0x1, SBF_B = 0x2, SBF_DW = 0x3 };

enum SBF_MODE {
SBF_IMM = 0x0,
Expand Down Expand Up @@ -82,16 +77,15 @@ static MCDisassembler *createSBFDisassembler(const Target &T,
return new SBFDisassembler(STI, Ctx);
}


extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSBFDisassembler() {
// Register the disassembler.
TargetRegistry::RegisterMCDisassembler(getTheSBFXTarget(),
createSBFDisassembler);
}

static const unsigned GPRDecoderTable[] = {
SBF::R0, SBF::R1, SBF::R2, SBF::R3, SBF::R4, SBF::R5,
SBF::R6, SBF::R7, SBF::R8, SBF::R9, SBF::R10, SBF::R11};
SBF::R0, SBF::R1, SBF::R2, SBF::R3, SBF::R4, SBF::R5,
SBF::R6, SBF::R7, SBF::R8, SBF::R9, SBF::R10, SBF::R11};

static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/,
Expand All @@ -105,8 +99,8 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
}

static const unsigned GPR32DecoderTable[] = {
SBF::W0, SBF::W1, SBF::W2, SBF::W3, SBF::W4, SBF::W5,
SBF::W6, SBF::W7, SBF::W8, SBF::W9, SBF::W10, SBF::W11};
SBF::W0, SBF::W1, SBF::W2, SBF::W3, SBF::W4, SBF::W5,
SBF::W6, SBF::W7, SBF::W8, SBF::W9, SBF::W10, SBF::W11};

static DecodeStatus
DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
Expand Down Expand Up @@ -146,12 +140,15 @@ static DecodeStatus readInstruction64(ArrayRef<uint8_t> Bytes, uint64_t Address,

Size = 8;
if (IsLittleEndian) {
Hi = (Bytes[0] << 24) | (Bytes[1] << 16) | (Bytes[2] << 0) | (Bytes[3] << 8);
Lo = (Bytes[4] << 0) | (Bytes[5] << 8) | (Bytes[6] << 16) | (Bytes[7] << 24);
Hi =
(Bytes[0] << 24) | (Bytes[1] << 16) | (Bytes[2] << 0) | (Bytes[3] << 8);
Lo =
(Bytes[4] << 0) | (Bytes[5] << 8) | (Bytes[6] << 16) | (Bytes[7] << 24);
} else {
Hi = (Bytes[0] << 24) | ((Bytes[1] & 0x0F) << 20) | ((Bytes[1] & 0xF0) << 12) |
(Bytes[2] << 8) | (Bytes[3] << 0);
Lo = (Bytes[4] << 24) | (Bytes[5] << 16) | (Bytes[6] << 8) | (Bytes[7] << 0);
Hi = (Bytes[0] << 24) | ((Bytes[1] & 0x0F) << 20) |
((Bytes[1] & 0xF0) << 12) | (Bytes[2] << 8) | (Bytes[3] << 0);
Lo =
(Bytes[4] << 24) | (Bytes[5] << 16) | (Bytes[6] << 8) | (Bytes[7] << 0);
}
Insn = Make_64(Hi, Lo);

Expand All @@ -167,7 +164,8 @@ DecodeStatus SBFDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
DecodeStatus Result;

Result = readInstruction64(Bytes, Address, Size, Insn, IsLittleEndian);
if (Result == MCDisassembler::Fail) return MCDisassembler::Fail;
if (Result == MCDisassembler::Fail)
return MCDisassembler::Fail;

uint8_t InstClass = getInstClass(Insn);
uint8_t InstMode = getInstMode(Insn);
Expand All @@ -178,10 +176,11 @@ DecodeStatus SBFDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
Result = decodeInstruction(DecoderTableSBFALU3264, Instr, Insn, Address,
this, STI);
else
Result = decodeInstruction(DecoderTableSBF64, Instr, Insn, Address, this,
STI);
Result =
decodeInstruction(DecoderTableSBF64, Instr, Insn, Address, this, STI);

if (Result == MCDisassembler::Fail) return MCDisassembler::Fail;
if (Result == MCDisassembler::Fail)
return MCDisassembler::Fail;

switch (Instr.getOpcode()) {
case SBF::LD_imm64:
Expand All @@ -192,25 +191,15 @@ DecodeStatus SBFDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
}
Size = 16;
if (IsLittleEndian)
Hi = (Bytes[12] << 0) | (Bytes[13] << 8) | (Bytes[14] << 16) | (Bytes[15] << 24);
Hi = (Bytes[12] << 0) | (Bytes[13] << 8) | (Bytes[14] << 16) |
(Bytes[15] << 24);
else
Hi = (Bytes[12] << 24) | (Bytes[13] << 16) | (Bytes[14] << 8) | (Bytes[15] << 0);
auto& Op = Instr.getOperand(1);
Hi = (Bytes[12] << 24) | (Bytes[13] << 16) | (Bytes[14] << 8) |
(Bytes[15] << 0);
auto &Op = Instr.getOperand(1);
Op.setImm(Make_64(Hi, Op.getImm()));
break;
}
case SBF::LD_ABS_B:
case SBF::LD_ABS_H:
case SBF::LD_ABS_W:
case SBF::LD_IND_B:
case SBF::LD_IND_H:
case SBF::LD_IND_W: {
auto Op = Instr.getOperand(0);
Instr.clear();
Instr.addOperand(MCOperand::createReg(SBF::R6));
Instr.addOperand(Op);
break;
}
}

return Result;
Expand Down
40 changes: 0 additions & 40 deletions llvm/lib/Target/SBF/SBFInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -896,48 +896,8 @@ let Constraints = "$dst = $src" in {
def BE32 : BSWAP<32, "be32", SBF_TO_BE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 32)))]>;
def BE64 : BSWAP<64, "be64", SBF_TO_BE, [(set GPR:$dst, (bswap GPR:$src))]>;
}
let Predicates = [SBFIsBigEndian] in {
def LE16 : BSWAP<16, "le16", SBF_TO_LE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 48)))]>;
def LE32 : BSWAP<32, "le32", SBF_TO_LE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 32)))]>;
def LE64 : BSWAP<64, "le64", SBF_TO_LE, [(set GPR:$dst, (bswap GPR:$src))]>;
}
}

let Defs = [R0, R1, R2, R3, R4, R5], Uses = [R6], hasSideEffects = 1,
hasExtraDefRegAllocReq = 1, hasExtraSrcRegAllocReq = 1, mayLoad = 1 in {
class LOAD_ABS<SBFWidthModifer SizeOp, string Mnemonic, Intrinsic OpNode>
: TYPE_LD_ST<SBF_ABS.Value, SizeOp.Value,
(outs),
(ins GPR:$skb, i64imm:$imm),
Mnemonic # " $imm",
[(set R0, (OpNode GPR:$skb, i64immSExt32:$imm))]> {
bits<32> imm;

let Inst{31-0} = imm;
let SBFClass = SBF_LD;
}

class LOAD_IND<SBFWidthModifer SizeOp, string Mnemonic, Intrinsic OpNode>
: TYPE_LD_ST<SBF_IND.Value, SizeOp.Value,
(outs),
(ins GPR:$skb, GPR:$val),
Mnemonic # " $val",
[(set R0, (OpNode GPR:$skb, GPR:$val))]> {
bits<4> val;

let Inst{55-52} = val;
let SBFClass = SBF_LD;
}
}

def LD_ABS_B : LOAD_ABS<SBF_B, "ldabsb", int_bpf_load_byte>;
def LD_ABS_H : LOAD_ABS<SBF_H, "ldabsh", int_bpf_load_half>;
def LD_ABS_W : LOAD_ABS<SBF_W, "ldabsw", int_bpf_load_word>;

def LD_IND_B : LOAD_IND<SBF_B, "ldindb", int_bpf_load_byte>;
def LD_IND_H : LOAD_IND<SBF_H, "ldindh", int_bpf_load_half>;
def LD_IND_W : LOAD_IND<SBF_W, "ldindw", int_bpf_load_word>;

let isCodeGenOnly = 1 in {
def MOV_32_64 : ALU_RR<SBF_ALU, SBF_MOV,
(outs GPR:$dst), (ins GPR32:$src),
Expand Down
4 changes: 0 additions & 4 deletions llvm/test/CodeGen/SBF/ninline_asm.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -9,10 +9,6 @@ entry:
%0 = bitcast i32* %a to i8*
call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %0) #2
store i32 4, i32* %a, align 4
tail call void asm sideeffect "ldabsh $0", "i"(i32 2) #2
; CHECK: ldabsh 2
tail call void asm sideeffect "ldindh $0", "r"(i32 4) #2
; CHECK: ldindh r1
%1 = tail call i32 asm sideeffect "mov64 $0, $1", "=r,i"(i32 4) #2
; CHECK: mov64 r1, 4
%2 = tail call i32 asm sideeffect "lddw $0, $1", "=r,i"(i64 333333333333) #2
Expand Down
6 changes: 0 additions & 6 deletions llvm/test/MC/Disassembler/SBF/sbf-alu.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -252,15 +252,9 @@



# CHECK-NEW: le16 r3
# CHECK-NEW: le32 r4
# CHECK-NEW: le64 r5
# CHECK-NEW: be16 r0
# CHECK-NEW: be32 r1
# CHECK-NEW: be64 r2
0xd4,0x03,0x00,0x00,0x10,0x00,0x00,0x00
0xd4,0x04,0x00,0x00,0x20,0x00,0x00,0x00
0xd4,0x05,0x00,0x00,0x40,0x00,0x00,0x00
0xdc,0x00,0x00,0x00,0x10,0x00,0x00,0x00
0xdc,0x01,0x00,0x00,0x20,0x00,0x00,0x00
0xdc,0x02,0x00,0x00,0x40,0x00,0x00,0x00
14 changes: 0 additions & 14 deletions llvm/test/MC/Disassembler/SBF/sbf-ldst.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -130,17 +130,3 @@
0xc3,0x58,0xf0,0xff,0xf1,0x00,0x00,0x00



# Obsolete ldabs/ldind for completeness.
# CHECK-NEW: ldabsb 64
# CHECK-NEW: ldabsh 128
# CHECK-NEW: ldabsw 0
# CHECK-NEW: ldindb r5
# CHECK-NEW: ldindh r9
# CHECK-NEW: ldindw r7
0x30,0x00,0x00,0x00,0x40,0x00,0x00,0x00
0x28,0x00,0x00,0x00,0x80,0x00,0x00,0x00
0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00
0x50,0x50,0x00,0x00,0x00,0x00,0x00,0x00
0x48,0x90,0x00,0x00,0x00,0x00,0x00,0x00
0x40,0x70,0x00,0x00,0x00,0x00,0x00,0x00
9 changes: 0 additions & 9 deletions llvm/test/MC/SBF/sbf-alu.s
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Original file line number Diff line number Diff line change
Expand Up @@ -330,21 +330,12 @@ mov32 w5, -123



# CHECK-OBJ-NEW: le16 r3
# CHECK-OBJ-NEW: le32 r4
# CHECK-OBJ-NEW: le64 r5
# CHECK-OBJ-NEW: be16 r0
# CHECK-OBJ-NEW: be32 r1
# CHECK-OBJ-NEW: be64 r2
# CHECK-ASM-NEW: encoding: [0xd4,0x03,0x00,0x00,0x10,0x00,0x00,0x00]
# CHECK-ASM-NEW: encoding: [0xd4,0x04,0x00,0x00,0x20,0x00,0x00,0x00]
# CHECK-ASM-NEW: encoding: [0xd4,0x05,0x00,0x00,0x40,0x00,0x00,0x00]
# CHECK-ASM-NEW: encoding: [0xdc,0x00,0x00,0x00,0x10,0x00,0x00,0x00]
# CHECK-ASM-NEW: encoding: [0xdc,0x01,0x00,0x00,0x20,0x00,0x00,0x00]
# CHECK-ASM-NEW: encoding: [0xdc,0x02,0x00,0x00,0x40,0x00,0x00,0x00]
le16 r3
le32 r4
le64 r5
be16 r0
be32 r1
be64 r2
21 changes: 0 additions & 21 deletions llvm/test/MC/SBF/sbf-ldst.s
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Original file line number Diff line number Diff line change
Expand Up @@ -183,24 +183,3 @@ stxxchgw [r8 - 16], w0
stxcmpxchgdw [r8 - 16], r5
stxcmpxchgw [r8 - 16], w5



# Obsolete ldabs/ldind for completeness.
# CHECK-OBJ-NEW: ldabsb 0x40
# CHECK-OBJ-NEW: ldabsh 0x80
# CHECK-OBJ-NEW: ldabsw 0
# CHECK-OBJ-NEW: ldindb r5
# CHECK-OBJ-NEW: ldindh r9
# CHECK-OBJ-NEW: ldindw r7
# CHECK-ASM-NEW: encoding: [0x30,0x00,0x00,0x00,0x40,0x00,0x00,0x00]
# CHECK-ASM-NEW: encoding: [0x28,0x00,0x00,0x00,0x80,0x00,0x00,0x00]
# CHECK-ASM-NEW: encoding: [0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
# CHECK-ASM-NEW: encoding: [0x50,0x50,0x00,0x00,0x00,0x00,0x00,0x00]
# CHECK-ASM-NEW: encoding: [0x48,0x90,0x00,0x00,0x00,0x00,0x00,0x00]
# CHECK-ASM-NEW: encoding: [0x40,0x70,0x00,0x00,0x00,0x00,0x00,0x00]
ldabsb 64
ldabsh 128
ldabsw 0
ldindb r5
ldindh r9
ldindw r7

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