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Implement unaligned memory accesses: LWL, LWR, SWL, SWR #132

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pavelkryukov opened this issue May 19, 2017 · 8 comments
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Implement unaligned memory accesses: LWL, LWR, SWL, SWR #132

pavelkryukov opened this issue May 19, 2017 · 8 comments
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2 Small features, tests coverage, simple laboratory works enhancement Adds a new feature to simulation. S1 — ISA To solve the issue, you need knowledge about MIPS or RISC-V ISA

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@pavelkryukov
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pavelkryukov commented May 19, 2017

Good explanation: https://www.cs.duke.edu/courses/cps104/fall02/homework/lwswlr.html

@pavelkryukov pavelkryukov added 2 Small features, tests coverage, simple laboratory works enhancement Adds a new feature to simulation. S1 — ISA To solve the issue, you need knowledge about MIPS or RISC-V ISA labels May 19, 2017
@pavelkryukov pavelkryukov added this to the Classic MIPS milestone Oct 8, 2017
@AndreiZoltan AndreiZoltan self-assigned this Apr 7, 2018
@pavelkryukov
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pavelkryukov commented Apr 16, 2018

Hi @AndrewSultan

I submitted a code review with updated infrastructure, which should support LWL instruction as well. I expect you to uncomment LWL instruction code in tt.core.s and check that my solution works. If not, please propose fixes.

Additionally, tt.core.s contains tests for ULW pseudo-instruction which is just LWL and LWR instructions in the same box. Please uncomment them too and see if it works.

Then, you may proceed by implementing SWL, SRW, and USW using the similar infrastructure.

I would highly appreciate if you create a Wiki page about those instructions, explaining them in a way you find most comfortable, however that is not mandatory.

@pavelkryukov
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@AndrewSultan

Additionally, it would be nice if you implemented unit tests for masked writes to RF.
See simulator/func_sim/rf/t/unit_tests.cpp for example and our Wiki manual

@AndreiZoltan
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First of all, we should add an addition condition in if in mipt_instr.cpp:
if ( operation == OUT_I_LOAD || operation == OUT_I_LOADR || operation == OUT_I_LOADL)
Secondly, change is_loadlr function:
return (operation == OUT_I_LOADR || operation == OUT_I_LOADL) ? 1 : 0;
But the tests still do not pass.

@AndreiZoltan
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0x402484: addiu $v0, $v0, 0xb9b4 [ $v0 = 0x42b9b4 ]
0x402488: or $v1, $zero, $zero [ $v1 = 0x0 ]
num = 0
val before lwl = 3020100
mask = ffffffff
val = ( val & mask) | ( static_cast(get_value( num)) & ~mask);
val after lwl = 3020100
0x40248c: lwl $v1, 0x0($v0) [ $v1 = 0x3020100]
0x402490: bne $v1, $zero, 289

@pavelkryukov
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pavelkryukov commented Apr 17, 2018

we should add an addition condition in if in mipt_instr.cpp:
if ( operation == OUT_I_LOAD || operation == OUT_I_LOADR || operation == OUT_I_LOADL

I performed it in a git branch. Please review the code in #397 .

@pavelkryukov
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LWL is fixed — please proceed with stores, documentation, and unit tests for masked writes.

@AndreiZoltan
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I'm going to write wiki a little bit later.

@pavelkryukov
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What about stores? I have not seen them operating

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