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Implement unaligned memory accesses: LWL, LWR, SWL, SWR #132
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Hi @AndrewSultan I submitted a code review with updated infrastructure, which should support LWL instruction as well. I expect you to uncomment LWL instruction code in Additionally, Then, you may proceed by implementing SWL, SRW, and USW using the similar infrastructure. I would highly appreciate if you create a Wiki page about those instructions, explaining them in a way you find most comfortable, however that is not mandatory. |
@AndrewSultan Additionally, it would be nice if you implemented unit tests for masked writes to RF. |
First of all, we should add an addition condition in if in mipt_instr.cpp: |
0x402484: addiu $v0, $v0, 0xb9b4 [ $v0 = 0x42b9b4 ] |
I performed it in a git branch. Please review the code in #397 . |
LWL is fixed — please proceed with stores, documentation, and unit tests for masked writes. |
I'm going to write wiki a little bit later. |
What about stores? I have not seen them operating |
Good explanation: https://www.cs.duke.edu/courses/cps104/fall02/homework/lwswlr.html
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