Add MIPS CP1 instructions to disassembler

[pavelkryukov]

FPU instructions are part of MIPS ISA (see part B). We want to start with instruction decoding only.

http://math-atlas.sourceforge.net/devel/assembly/mips-iv.pdf

Use our current MIPS disassembler code to introduce the floating point instructions.

[pavelkryukov]

@DavidRabbitson
The best way to generate unit tests is to:

1. Uncomment FPU instructions in https://github.com/MIPT-ILab/mips-traces/blob/master/tt.core.universal.s
2. Build the file with MIPS assembler
3. Dump its contents with MIPS objdump (mips-unknown-gnu-linux-objdump -d filename.out)

Then you can implement the code in TDD manner.

[bova-ev]

Ok. Now I'm learning FPU's instructions structure. First enhancements will be on these weekends.

[bova-ev]

How do I add instructions to mips_instr.cpp like add.s and add.d if they have the same function code?

[pavelkryukov]

For example, you can add different tables for different formats

[bova-ev]

How do I add tables to the decoder if instructions with COP1=0x11 opcode have different defining fields?

mipt-mips/simulator/mips/mips_instr.cpp

Lines 378 to 385 in 0d6542a

	switch ( instr.opcode)
	{
	case 0x0: return get_table_entry( isaMapR<I>, instr.funct);
	case 0x1: return get_table_entry( isaMapRI<I>, instr.rt);
	case 0x10: return get_table_entry( isaMapCOP0<I>, instr.rs);
	case 0x1C: return get_table_entry( isaMapMIPS32<I>, instr.funct);
	default: return get_table_entry( isaMapIJ<I>, instr.opcode);
	}

I mean instruction add.s is defined by the funct field and bc1f is defined by the fmt/rs field.

[pavelkryukov]

I think it may be handled in a separate method where you can check functors etc.

 switch ( instr.opcode) 
 { 
     case 0x0:  return get_table_entry( isaMapR<I>,      instr.funct); 
     case 0x1:  return get_table_entry( isaMapRI<I>,     instr.rt); 
     case 0x10: return get_table_entry( isaMapCOP0<I>,   instr.rs);
     case 0x11: return get_cp1_entry( instr); 
     case 0x1C: return get_table_entry( isaMapMIPS32<I>, instr.funct); 
     default:   return get_table_entry( isaMapIJ<I>,     instr.opcode); 
 }

By the way, may you check-in the tests, even if they are disabled for now?

[bova-ev]

How can I define the same instruction if in MIPS I it does not have any inputs except offset and in MIPS IV it has one more input?

[pavelkryukov]

cc = 0 implied means that it is implied by compiler or assembler. We have to implement the generic case.

[bova-ev]

Instructions mfc1 and mtc1 have the same order of arguments rt, fs, but in first case rt is destination and in second is source. Can I reorder them like in mtc0 and mfc0 case or should I make them like reference says?

mipt-mips/simulator/mips/t/unit_test.cpp

Line 2056 in ea14ec1

CHECK(MIPS32Instr(0x408d2000).get_disasm() == "mfc0 $a0, $Cause");

mipt-mips/simulator/mips/t/unit_test.cpp

Line 2180 in ea14ec1

CHECK(MIPS32Instr(0x40046800).get_disasm() == "mtc0 $Cause, $a0");

[pavelkryukov]

I prefer to stick to our conventions where destination always goes first, and sources follow it.

[pavelkryukov]

• lwc1
• swc1
• ldc1
• sdc1
• lwxc1
• swxc1
• ldxc1
• sdxc1
• mtc1
• mfc1
• dmtc1
• dmfc1
• ctc1
• cfc1
• add
• sub
• mul
• div
• abs
• neg
• sqrt
• c
• recip
• rsqrt
• madd
• msub
• nmadd
• nmsub
• cvt
• round
• trunc
• ceil
• floor
• mov
• movt
• movf
• movz
• movn
• bc1t
• bc1f
• bc1tl
• bc1tf

[bova-ev]

Oh, thats better.

[bova-ev]

How can I add Src3 to implement madd.fmt instructions? I don't feel that adding src3 here is good idea.

mipt-mips/simulator/mips/mips_instr.cpp

Lines 228 to 230 in 8d9569a

	template<typename I>
	struct MIPSTableEntry
	{

[pavelkryukov]

Ouch. Let's put these instructions aside for now.

[bova-ev]

Do I need to implement 3rd source print?

[pavelkryukov]

Yes, I think that would be useful