Convert torture tests to unit tests

[pavelkryukov]

Blocked by #589

To test functionality of instruction, we use SPIM torture tests (TT). That is not very convinient, as we have to build Binutils and traces in addition to unit tests. The idea is to convert the TT test cases into unit test cases.

Example:

	li $2, 1
	li $4, 0
	sllv $3, $2, $4
	bne $3, 1, fail

becomes

TEST_CASE("sllv")
{
    MIPSInstr<MIPS32> instr( "sllv"); // You need #589 to do that
    instr.set_v_src1( 1);
    instr.set_v_src2( 0);
    instr.execute();
    CHECK( instr.get_v_dst(), 1);
}

There are about 120 instructions supported by MIPT-MIPS so far.
Let's assume that adding tests for 17 instructions is a 1 point, so adding tests to 119 instructions is 7 points. You are not obliged to get all the 7 points at once, you may make 1 point and stop, then continue later or pass the task to another project participant.

[pavelkryukov]

Just to clarify: torture tests are located here: https://github.com/MIPT-ILab/mips-traces/blob/master/tt.core.universal.s

[pavelkryukov]

@pooh64 What's the progress with that?

[pukhovv]

@pavelkryukov Now I'm learning mips assembler, I haven't written new tests yet.

[pukhovv]

Implemented, but not tested instructions:

1. beql
2. bgez
3. bgezal
4. bgezall
5. bgezl
6. bgtz
7. bgtzl
8. blez
9. blezl
10. bltz
11. bltzal
12. bltzall
13. bltzl
14. bnel

[bova-ev]

@pavelkryukov Can I write to the HI and LO registers that are used as destination registers in instruction madd (for example)? As I can see I can change only one destination register by using instr.set_v_dst() function.

[bova-ev]

Also I see that every load_store instruction is running at both 32 bit and 64 bit systems. Do I need to test them in 64 bit as well?

[pavelkryukov]

There is some discrepancy between the behavior in 32 bit and 64 bit mode.
I do not remember what is the point, but I suspecte it is related to sign extension.
Could you please tell what is different in 32 bit and 64 bit tests?

[bova-ev]

I'm not sure if this is significant difference but in 32 bit MIPS sign extended value we get after lb (0xab should be loaded) is 0xffff'ffab and in 64 bit it is 0xffff'ffff'ffff'ffab just because GPR [rt] is 64 bit long.

[pavelkryukov]

Ok, I agree that difference may be ignored in unit tests. The issue was that MIPS code has to use different immediates.

[pavelkryukov]

Leaving 2 points as 2 points were committed to the score table.

[bova-ev]

@pavelkryukov ll instruction provides primitives to implement atomic Read-Modify-Write (RMW) operations for cached memory locations. How can I test this RMW part of this instruction? Or I can do ll tests similar to lh tests?

[pavelkryukov]

We do not have a data cache model so far, therefore it should behave like a simple load of the similar size.

[bova-ev]

ldr and ldl instructions returns the same result with same arguments. I think problem is located here:

mipt-mips/simulator/mips/mips_instr.cpp

Lines 76 to 77 in 8a2335b

	template<typename I> auto mips_ldl = ALU::load_addr<I>;
	template<typename I> auto mips_ldr = ALU::load_addr<I>;

Do I need to fix this or this is ok?

[pavelkryukov]

If you are able to write manual on these instructions (#413), then you can implement them. But at the moment, we should just skip them, since they are not implemented.

[bova-ev]

How can I read memory created by this function?

mipt-mips/simulator/mips/t/unit_test.cpp

Lines 1065 to 1070 in 8bcc2a3

	static auto get_plain_memory_with_data()
	{
	auto memory = FuncMemory::create_plain_memory(15);
	memory->write<uint32, Endian::little>( 0xABCD'1234, 0x1000);
	return memory;
	}

[pavelkryukov]

auto m = get_plain_memory_with_data();
auto value = m->read<uint32, Endian::little>( address);

[bova-ev]

Can I write templates in unit_test.cpp?

[pavelkryukov]

Yes, but could you please share your intention? I don't feel there is a good idea...

[bova-ev]

@pavelkryukov Why do I get dst = 0xdeadbeef when I test bgezal -1? Shouldn't I get dst = PC + 8?

[pavelkryukov]

Looks like a bug — $ra should be updated regardless of branch being taken or not taken.
Could you please fix it?

[bova-ev]

Does likely branches do the same thing in simulator as basic branches?

[pavelkryukov]

Likely branches are not supported at the moment, so you may write tests but probably they won't pass. The general idea is that likely branches do not execute delay slot instruction.