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Use faster C++11 STL container for MIPS ISA #69

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pavelkryukov opened this issue Apr 10, 2017 · 12 comments
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Use faster C++11 STL container for MIPS ISA #69

pavelkryukov opened this issue Apr 10, 2017 · 12 comments
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1 Usually one-liner tasks, but may require some deep into infrastructure. code Enhances infrastructure or refines, Requires almost no knowledge in CPU microarchitecture. S1 — ISA To solve the issue, you need knowledge about MIPS or RISC-V ISA

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@pavelkryukov
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Currently MIPS ISA is stored in C-style static array. With C++11 we may initialize something like std::list or std::unordered_map during compile-time.

@pavelkryukov pavelkryukov added 1 Usually one-liner tasks, but may require some deep into infrastructure. code Enhances infrastructure or refines, Requires almost no knowledge in CPU microarchitecture. labels Apr 10, 2017
@pavelkryukov pavelkryukov added the S1 — ISA To solve the issue, you need knowledge about MIPS or RISC-V ISA label Apr 26, 2017
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pavelkryukov commented Oct 15, 2017

@TimofeevAlex I would like to see 3 std::unordered_maps. If opcode is 0x0, search is performed over map of R-instructions. If opcode is 0x1, search is performed over map of RI-instructions (so it is a good opportunity to close issues #93 and #137 and get 5 more points!). Otherwise, search is performed over map of I- and J-instructions. You may skip RI-instructions for now, as they are not implemented yet.

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@TimofeevAlex Any progress?

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TimofeevAlex commented Oct 23, 2017 via email

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@TimofeevAlex Ok, thank you for notification. I advise you to finish it next week as we have a MIPS ISA lecture in the beginning of November, so other guys may implement missing MIPS instructions, creating merge conflicts for you.

@pavelkryukov pavelkryukov modified the milestones: Simulation Speed, RISC-V Oct 25, 2017
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@TimofeevAlex Any progress?

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TimofeevAlex commented Nov 1, 2017 via email

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pavelkryukov commented Nov 1, 2017

That's great!

I think we should use std::unordered_map here as it has O(1) read time.
Currently we have this:

for ( const auto& entry : isaTable)
{
    bool is_i_R = ( entry.format == FORMAT_R);
    if ( entry.opcode == ident && ( is_i_R == is_R))
    {
          // instruction initialization

And we want to get here (at least, you may do something better. like adding instruction format instead of bool to the key):

const auto& entry = isaTable.find( std::make_pair( opcode, is_R));
if ( entry != isaTable.end())
{
     // instruction initialization

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Feel free to ask questions

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TimofeevAlex commented Nov 1, 2017 via email

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pavelkryukov commented Nov 8, 2017

One week passed since our previous sync-up. Do you have any updates on the issue?

@pavelkryukov pavelkryukov modified the milestones: RISC-V, Simulation Speed Nov 9, 2017
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One more week passed since our previous sync-up. Do you have any updates on the issue? Kirill is working on #93, he might proceed faster with that issue.

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TimofeevAlex commented Nov 16, 2017 via email

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1 Usually one-liner tasks, but may require some deep into infrastructure. code Enhances infrastructure or refines, Requires almost no knowledge in CPU microarchitecture. S1 — ISA To solve the issue, you need knowledge about MIPS or RISC-V ISA
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