Implement RISC-V M instructions

[pavelkryukov]

RISC-V ISA has 'M' extension for multiplication and division instructions. We currently decode them, but we do not execute them. Your objective is to implement the executors in https://github.com/MIPT-ILab/mipt-mips/blob/master/simulator/risc_v/riscv_instr.cpp and https://github.com/MIPT-ILab/mipt-mips/tree/master/simulator/func_sim/multiplication.h.

To test instructions, enable these FuncSim tests

mipt-mips/simulator/func_sim/t/unit_test.cpp

Lines 291 to 323 in 7081e8e

	// See tracker #925
	#if 0
	TEST_CASE( "Torture_Test: rv32um")
	{
	CHECK( riscv_torture_test_passes("riscv32", RISCV_TEST_PATH "/isa/rv32um-p-div") );
	CHECK( riscv_torture_test_passes("riscv32", RISCV_TEST_PATH "/isa/rv32um-p-divu") );
	CHECK( riscv_torture_test_passes("riscv32", RISCV_TEST_PATH "/isa/rv32um-p-mul") );
	CHECK( riscv_torture_test_passes("riscv32", RISCV_TEST_PATH "/isa/rv32um-p-mulh") );
	CHECK( riscv_torture_test_passes("riscv32", RISCV_TEST_PATH "/isa/rv32um-p-mulhsu") );
	CHECK( riscv_torture_test_passes("riscv32", RISCV_TEST_PATH "/isa/rv32um-p-mulhu") );
	CHECK( riscv_torture_test_passes("riscv32", RISCV_TEST_PATH "/isa/rv32um-p-rem") );
	CHECK( riscv_torture_test_passes("riscv32", RISCV_TEST_PATH "/isa/rv32um-p-remu") );
	}
	TEST_CASE( "Torture_Test: rv64um")
	{
	CHECK( riscv_torture_test_passes("riscv32", RISCV_TEST_PATH "/isa/rv64um-p-div") );
	CHECK( riscv_torture_test_passes("riscv32", RISCV_TEST_PATH "/isa/rv64um-p-divu") );
	CHECK( riscv_torture_test_passes("riscv32", RISCV_TEST_PATH "/isa/rv64um-p-divuw") );
	CHECK( riscv_torture_test_passes("riscv32", RISCV_TEST_PATH "/isa/rv64um-p-divw") );
	CHECK( riscv_torture_test_passes("riscv32", RISCV_TEST_PATH "/isa/rv64um-p-mul") );
	CHECK( riscv_torture_test_passes("riscv32", RISCV_TEST_PATH "/isa/rv64um-p-mulh") );
	CHECK( riscv_torture_test_passes("riscv32", RISCV_TEST_PATH "/isa/rv64um-p-mulhsu") );
	CHECK( riscv_torture_test_passes("riscv32", RISCV_TEST_PATH "/isa/rv64um-p-mulhu") );
	CHECK( riscv_torture_test_passes("riscv32", RISCV_TEST_PATH "/isa/rv64um-p-mulw") );
	CHECK( riscv_torture_test_passes("riscv32", RISCV_TEST_PATH "/isa/rv64um-p-rem") );
	CHECK( riscv_torture_test_passes("riscv32", RISCV_TEST_PATH "/isa/rv64um-p-remu") );
	CHECK( riscv_torture_test_passes("riscv32", RISCV_TEST_PATH "/isa/rv64um-p-remuw" );
	CHECK( riscv_torture_test_passes("riscv32", RISCV_TEST_PATH "/isa/rv64um-p-remw") );
	}
	#endif

For reference, see RISC-V ISA document: https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf or in Google.

[vodogrey2012]

Hello. As I see now, this tests were removed in 124f38a commit. Should I put it back to .../risc_v/unit_test.cpp ?

[pavelkryukov]

There are 2 options:

1. Put the M tests back to FuncSim tests, that should work fine.
2. More advanced: copy tests macro from these files https://github.com/MIPT-ILab/riscv-tests-prebuilt/tree/master/isa/rv64um to that file https://github.com/MIPT-ILab/mipt-mips/blob/master/simulator/risc_v/t/riscv64_test.cpp. It is nicer since we do not have to run FuncSim to test implementations, and we do not need prebuilt binary files.

[vodogrey2012]

Hello. When I add prebuilt tests for mulhu, for example, it causes this:

/home/yauheni/programs/mips/mipt-mips/simulator/risc_v/t/riscv64_test.cpp:1260:44: error: left shift count >= width of type [-Werror=shift-count-overflow]
   TEST_RR_SRC1_EQ_DEST( 8, mulhu, 143, 13<<32, 11<<32 )

this solves by adding UL : 13UL<<32.
But in case that in parent repo there is now information about it, I am not sure is it a bug or my fault?
Thank you.

[pavelkryukov]

Your fix is correct. The original repo is not a C++ code, so they may have these glitches.