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1. LAB1-Ubuntu-install LAB1-Ubuntu-install Public

   Jupyter Notebook

2. Lab2-MAXI-and-Stream-interface- Lab2-MAXI-and-Stream-interface- Public

   用HLS 實作 MAXI and Stream interface 不同

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3. Lab3-MAXI-and-Stream-interface-with-BRAM-in-verilog-in-FPGA Lab3-MAXI-and-Stream-interface-with-BRAM-in-verilog-in-FPGA Public

   Verilog

4. LAB4-0-caravel-SOC-simulation- LAB4-0-caravel-SOC-simulation- Public

   建立caravel SOC simulation 環境

5. LAB4-2-MIX-LAB3-FIR-LAB4-1-WITH-WISHBOND LAB4-2-MIX-LAB3-FIR-LAB4-1-WITH-WISHBOND Public

   結合LAB3 fir & LAB4-1 exemem-fir，放入user project area 用WB(wishbond interface)作為user project & caravel soc溝通介面

   Verilog

6. LAB4-1-Firmware-User-project LAB4-1-Firmware-User-project Public

   * 利用firmware控制user project 並且執行 * firmware Code input "exmem" 並且執行

   Verilog