use chisel version 6.2.0

Martoni · Mar 7, 2024 · 8a655a2 · 8a655a2
1 parent ae864fc
commit 8a655a2
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diff --git a/README.md b/README.md
@@ -1,5 +1,5 @@
 # FpgaMacro
-A Chisel3 package to describe verilog FPGA template and macro for hardened FPGA modules
+A [Chisel](https://www.chisel-lang.org/) package to describe verilog FPGA template and macro for hardened FPGA modules
 
 # Install
 
@@ -14,7 +14,7 @@ $ sbt publishLocal
 Then add these lines in your `build.sbt` project :
 ```scala
 //publish local https://github.com/Martoni/fpgamacro.git
-libraryDependencies ++= Seq("org.armadeus" %% "fpgamacro" % "0.2.2")
+libraryDependencies ++= Seq("org.armadeus" %% "fpgamacro" % "6.2.0")
 ```
 
 # Library

diff --git a/build.sbt b/build.sbt
@@ -5,7 +5,7 @@ version          := "6.1.0"
 organization     := "Martoni"
 
 val majorChiselVersion = "6"
-val minorChiselVersion = "1.0"
+val minorChiselVersion = "2.0"
 
 val chiselVersion = majorChiselVersion + "." + minorChiselVersion