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  • The University of Texas at Austin
  • Austin, TX

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  1. RTL-IP RTL-IP Public

    Various RTL blocks I use in my FPGA based projects

    SystemVerilog

  2. RTOS-from-scratch RTOS-from-scratch Public

    A humble attempt to implement a homemade RTOS on various embedded platforms

    C

  3. Drop-In-JTAG Drop-In-JTAG Public archive

    Open Source Silicon Development Testing Unit - Senior Design Project

    SystemVerilog 1 1

  4. cvw cvw Public archive

    Forked from openhwgroup/cvw

    CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…

    C 1

  5. OKState-TWISTER/TWISTER-Automation-Library OKState-TWISTER/TWISTER-Automation-Library Public

    A set of standardized classes and functions used to interface with the TWISTER system

    Python 1

  6. FAST-Research-Group/primate-uarch FAST-Research-Group/primate-uarch Public

    Forked from seyedmaysamlavasani/GorillaPP

    Primate Microarchitecture ~ Based on Gorilla++: https://github.com/seyedmaysamlavasani/GorillaPP

    Verilog