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hw-mgmt: patches: Update SN4280 platform driver
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This patch removes the reset_from_carrier reset
reason as it is assserted for every power cycle
and watchdog reboots.

Bug #3981606

Signed-off-by: Ciju Rajan K <crajank@nvidia.com>
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@ciju-nvidia
ciju-nvidia committed Jul 9, 2024
1 parent 2704fd0 commit 7ff4739
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Showing 2 changed files with 47 additions and 59 deletions.
54 changes: 24 additions & 30 deletions ...s-kernel/linux/linux-5.10/0335-platform-mellanox-Introduce-support-of-Nvidia-smart-.patch
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Original file line number Diff line number Diff line change
Expand Up @@ -23,11 +23,11 @@ activation of the required platform drivers.

Signed-off-by: Vadim Pasternak <vadimp@nvidia.com>
---
drivers/platform/mellanox/mlx-platform.c | 933 ++++++++++++++++++++++++++++---
1 file changed, 866 insertions(+), 67 deletions(-)
drivers/platform/mellanox/mlx-platform.c | 927 +++++++++++++++++++++--
1 file changed, 860 insertions(+), 67 deletions(-)

diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c
index 785f5870d..896e687b0 100644
index 785f5870d..e3cef3c6d 100644
--- a/drivers/platform/mellanox/mlx-platform.c
+++ b/drivers/platform/mellanox/mlx-platform.c
@@ -40,6 +40,7 @@
Expand Down Expand Up @@ -357,7 +357,7 @@ index 785f5870d..896e687b0 100644
/* Callback performs graceful shutdown after notification about power button event */
static int
mlxplat_mlxcpld_l1_switch_pwr_events_handler(void *handle, enum mlxreg_hotplug_kind kind,
@@ -5655,99 +5883,579 @@ static struct mlxreg_core_platform_data mlxplat_chassis_blade_regs_io_data = {
@@ -5655,99 +5883,573 @@ static struct mlxreg_core_platform_data mlxplat_chassis_blade_regs_io_data = {
.counter = ARRAY_SIZE(mlxplat_mlxcpld_chassis_blade_regs_io_data),
};

Expand Down Expand Up @@ -595,12 +595,6 @@ index 785f5870d..896e687b0 100644
+ .mode = 0444,
+ },
+ {
+ .label = "reset_from_carrier",
+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(1),
+ .mode = 0444,
+ },
+ {
+ .label = "reset_aux_pwr_or_reload",
+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(2),
Expand Down Expand Up @@ -1003,7 +997,7 @@ index 785f5870d..896e687b0 100644
.reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET,
.mask = GENMASK(7, 0),
.capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
@@ -6302,6 +7010,8 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
@@ -6302,6 +7004,8 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET:
Expand All @@ -1012,15 +1006,15 @@ index 785f5870d..896e687b0 100644
case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET:
case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
@@ -6317,6 +7027,7 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
@@ -6317,6 +7021,7 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET:
case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:
case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_GP3_OFFSET:
case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE:
case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET:
case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET:
@@ -6344,8 +7055,10 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
@@ -6344,8 +7049,10 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
case MLXPLAT_CPLD_LPC_REG_ASIC4_MASK_OFFSET:
case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
Expand All @@ -1031,7 +1025,7 @@ index 785f5870d..896e687b0 100644
case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
case MLXPLAT_CPLD_LPC_REG_FAN2_EVENT_OFFSET:
@@ -6421,6 +7134,8 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
@@ -6421,6 +7128,8 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
case MLXPLAT_CPLD_LPC_REG_CPLD6_PN_OFFSET:
case MLXPLAT_CPLD_LPC_REG_CPLD6_PN1_OFFSET:
case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET:
Expand All @@ -1040,7 +1034,7 @@ index 785f5870d..896e687b0 100644
case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET:
case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
@@ -6436,12 +7151,14 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
@@ -6436,12 +7145,14 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION:
case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET:
case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET:
Expand All @@ -1055,15 +1049,15 @@ index 785f5870d..896e687b0 100644
case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE:
case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET:
case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET:
@@ -6461,6 +7178,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
@@ -6461,6 +7172,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET:
case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET:
case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_GPI_MASK_OFFSET:
case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET:
case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET:
case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET:
@@ -6479,9 +7197,11 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
@@ -6479,9 +7191,11 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET:
case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
Expand All @@ -1075,7 +1069,7 @@ index 785f5870d..896e687b0 100644
case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET:
case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
@@ -6607,6 +7327,8 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
@@ -6607,6 +7321,8 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
case MLXPLAT_CPLD_LPC_REG_CPLD6_PN_OFFSET:
case MLXPLAT_CPLD_LPC_REG_CPLD6_PN1_OFFSET:
case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET:
Expand All @@ -1084,7 +1078,7 @@ index 785f5870d..896e687b0 100644
case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET:
case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
@@ -6622,10 +7344,12 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
@@ -6622,10 +7338,12 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION:
case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET:
case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET:
Expand All @@ -1097,15 +1091,15 @@ index 785f5870d..896e687b0 100644
case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE:
case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET:
case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET:
@@ -6645,6 +7369,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
@@ -6645,6 +7363,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET:
case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET:
case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_GPI_MASK_OFFSET:
case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET:
case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET:
case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET:
@@ -6663,9 +7388,11 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
@@ -6663,9 +7382,11 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET:
case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
Expand All @@ -1117,7 +1111,7 @@ index 785f5870d..896e687b0 100644
case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET:
case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
@@ -6816,6 +7543,15 @@ static const struct reg_default mlxplat_mlxcpld_regmap_eth_modular[] = {
@@ -6816,6 +7537,15 @@ static const struct reg_default mlxplat_mlxcpld_regmap_eth_modular[] = {
MLXPLAT_CPLD_AGGR_MASK_LC_LOW },
};

Expand All @@ -1133,7 +1127,7 @@ index 785f5870d..896e687b0 100644
struct mlxplat_mlxcpld_regmap_context {
void __iomem *base;
};
@@ -6924,6 +7660,20 @@ static const struct regmap_config mlxplat_mlxcpld_regmap_config_eth_modular = {
@@ -6924,6 +7654,20 @@ static const struct regmap_config mlxplat_mlxcpld_regmap_config_eth_modular = {
.reg_write = mlxplat_mlxcpld_reg_write,
};

Expand All @@ -1154,15 +1148,15 @@ index 785f5870d..896e687b0 100644
/* Wait completion routine for indirect access for register map */
static int mlxplat_fpga_completion_wait(struct mlxplat_mlxcpld_regmap_context *ctx)
{
@@ -7043,6 +7793,7 @@ static struct mlxreg_core_platform_data *mlxplat_regs_io;
@@ -7043,6 +7787,7 @@ static struct mlxreg_core_platform_data *mlxplat_regs_io;
static struct mlxreg_core_platform_data *mlxplat_fan;
static struct mlxreg_core_platform_data
*mlxplat_wd_data[MLXPLAT_CPLD_WD_MAX_DEVS];
+static struct mlxreg_core_data *mlxplat_dpu_data[MLXPLAT_CPLD_DPU_MAX_DEVS];
static const struct regmap_config *mlxplat_regmap_config;
static struct spi_board_info *mlxplat_spi;
static struct pci_dev *lpc_bridge;
@@ -7496,6 +8247,29 @@ static int __init mlxplat_dmi_xdr_matched(const struct dmi_system_id *dmi)
@@ -7496,6 +8241,29 @@ static int __init mlxplat_dmi_xdr_matched(const struct dmi_system_id *dmi)
return mlxplat_register_platform_device();
}

Expand Down Expand Up @@ -1192,7 +1186,7 @@ index 785f5870d..896e687b0 100644
static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
{
.callback = mlxplat_dmi_default_wc_matched,
@@ -7609,6 +8383,12 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
@@ -7609,6 +8377,12 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
DMI_MATCH(DMI_BOARD_NAME, "VMOD0018"),
},
},
Expand All @@ -1205,7 +1199,7 @@ index 785f5870d..896e687b0 100644
{
.callback = mlxplat_dmi_msn274x_matched,
.matches = {
@@ -7910,7 +8690,7 @@ static void mlxplat_post_exit(void)
@@ -7910,7 +8684,7 @@ static void mlxplat_post_exit(void)

static int mlxplat_post_init(struct mlxplat_priv *priv)
{
Expand All @@ -1214,7 +1208,7 @@ index 785f5870d..896e687b0 100644

/* Add hotplug driver */
if (mlxplat_hotplug) {
@@ -7990,8 +8770,25 @@ static int mlxplat_post_init(struct mlxplat_priv *priv)
@@ -7990,8 +8764,25 @@ static int mlxplat_post_init(struct mlxplat_priv *priv)
}
}

Expand All @@ -1240,7 +1234,7 @@ index 785f5870d..896e687b0 100644
fail_platform_wd_register:
while (--i >= 0)
platform_device_unregister(priv->pdev_wd[i]);
@@ -8012,6 +8809,8 @@ static void mlxplat_pre_exit(struct mlxplat_priv *priv)
@@ -8012,6 +8803,8 @@ static void mlxplat_pre_exit(struct mlxplat_priv *priv)
{
int i;

Expand All @@ -1250,5 +1244,5 @@ index 785f5870d..896e687b0 100644
platform_device_unregister(priv->pdev_wd[i]);
if (priv->pdev_fan)
--
2.14.1
2.44.0

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