This is a Board Support Package in form of a Vivado project for DAMC-TCK7. It serves as a demonstration of board features and as a starting point for custom developments.
This project is maintained by MicroTCA Technology Lab at DESY.
Xilinx driver: AR# 65444
The on-board oscillator are configured by a MicroBlaze processor upon start-up. Because the Xilinx IBERT core does not have a reset connection, it starts before the oscillators are configured, which results in QPLLs in MGTs (COMMON_X0Y2/QPLL_0 and COMMON_X0Y3/QPLL_0) not being locked.
Is is necessary to reset the QPLLs by writing 1 and then 0 to PORT.QPLLRESET in both QPLLs. Another alternative solution is to configure the FPGA for the second time; the oscillators are already stable at this point and the QPLLs will lock.
This project requires Vivado version 2019.1
In Vivado:
cd
into project dirsource ../scripts/recreate.tcl
source ../scripts/bd.tcl
source ../scripts/wrapper.tcl
To compile the project:
launch_runs impl_1 -to_step write_bitstream -jobs 4
- Grab a coffee, this is going to take some time
- Create block diagram and it's wrapper (see "Recreating project")
- From Vivado open SDK (File -> Launch SDK)
- For Exported location select
<TOP>/exported_hw
, for Workspace select<TOP>/sdk
- Xilinx SDK will open
- Import project: File -> Import -> Existing Projects into Workspace
- Select root directory: to
<TOP>/sdk
- Make sure that both
tck7_board_controller
andtck7_board_controller_bsp
are selected - Press Finish
From project dir:
write_bd_tcl -include_layout -force ../scripts/bd.tcl
- Copy generated .elf into
<TOP>/sdk/elf
- Add .elf to Vivado project
- Set parameters
SCOPED_TO_CELLS
tomicroblaze_0
andSCOPED_TO_REF
tosystem
If you need to update recrete.tcl, run:
write_project_tcl -use_bd_files -force ../scripts/recreate.tcl
Please be careful as there are some hand-crafted modification in recreate.tcl