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Adding support for Microchip PIC32CX SG devices
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@MyGh64605
MyGh64605 committed Jun 18, 2024
1 parent 1bf0f21 commit 22f2a0d
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Showing 5 changed files with 28 additions and 58 deletions.
2 changes: 1 addition & 1 deletion mplabx/pic32cxsg/include/pic32cxsg41/component/dac.h
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Expand Up @@ -188,7 +188,7 @@ typedef union {
uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */
uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */
uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */
uint8_t Reserved1:1 /*!< bit: 4 Result 0 Ready Interrupt Enable */
uint8_t Reserved1:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */
uint8_t Reserved2:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */
uint8_t Reserved3:1; /*!< bit: 6 Overrun 0 Interrupt Enable */
uint8_t Reserved4:1; /*!< bit: 7 Overrun 1 Interrupt Enable */
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45 changes: 11 additions & 34 deletions mplabx/pic32cxsg/include/pic32cxsg41/component/nvmctrl.h
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Expand Up @@ -398,23 +398,20 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register

/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x12) ( R/ 16) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
typedef union {
struct {
__I uint16_t DONE:1; /*!< bit: 0 Command Done */
__I uint16_t ADDRE:1; /*!< bit: 1 Address Error */
__I uint16_t PROGE:1; /*!< bit: 2 Programming Error */
__I uint16_t LOCKE:1; /*!< bit: 3 Lock Error */
__I uint16_t ECCSE:1; /*!< bit: 4 ECC Single Error */
__I uint16_t ECCDE:1; /*!< bit: 5 ECC Dual Error */
__I uint16_t NVME:1; /*!< bit: 6 NVM Error */
__I uint16_t SUSP:1; /*!< bit: 7 Suspended Write Or Erase Operation */
__I uint16_t SEESFULL:1; /*!< bit: 8 Active SEES Full */
__I uint16_t SEESOVF:1; /*!< bit: 9 Active SEES Overflow */
__I uint16_t SEEWRC:1; /*!< bit: 10 SEE Write Completed */
__I uint16_t :5; /*!< bit: 11..15 Reserved */
uint16_t READY:1; /*!< bit: 0 Ready to accept a command */
uint16_t PRM:1; /*!< bit: 1 Power Reduction Mode */
uint16_t LOAD:1; /*!< bit: 2 NVM Page Buffer Active Loading */
uint16_t SUSP:1; /*!< bit: 3 NVM Write Or Erase Operation Is Suspended */
uint16_t AFIRST:1; /*!< bit: 4 BANKA First */
uint16_t BPDIS:1; /*!< bit: 5 Boot Loader Protection Disable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t BOOTPROT:4; /*!< bit: 8..11 Boot Loader Protection Size */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} NVMCTRL_INTFLAG_Type;
} NVMCTRL_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define NVMCTRL_STATUS_RESETVALUE _UINT16_(0x00) /* (NVMCTRL_STATUS) Status Reset Value */
Expand Down Expand Up @@ -641,7 +638,6 @@ typedef union {
#define NVMCTRL_SEECFG_APRDIS(value) (NVMCTRL_SEECFG_APRDIS_Msk & (_UINT8_(value) << NVMCTRL_SEECFG_APRDIS_Pos)) /* Assigment of value for APRDIS in the NVMCTRL_SEECFG register */
#define NVMCTRL_SEECFG_Msk _UINT8_(0x03) /* (NVMCTRL_SEECFG) Register Mask */


/* -------- NVMCTRL_SEESTAT : (NVMCTRL Offset: 0x2C) ( R/ 32) SmartEEPROM Status Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
Expand Down Expand Up @@ -703,24 +699,6 @@ typedef union {
#define NVMCTRL_SEECFG_REG_OFST _UINT32_(0x2A) /* (NVMCTRL_SEECFG) SmartEEPROM Configuration Register Offset */
#define NVMCTRL_SEESTAT_REG_OFST _UINT32_(0x2C) /* (NVMCTRL_SEESTAT) SmartEEPROM Status Register Offset */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ASEES:1; /*!< bit: 0 Active SmartEEPROM Sector */
uint32_t LOAD:1; /*!< bit: 1 Page Buffer Loaded */
uint32_t BUSY:1; /*!< bit: 2 Busy */
uint32_t LOCK:1; /*!< bit: 3 SmartEEPROM Write Access Is Locked */
uint32_t RLOCK:1; /*!< bit: 4 SmartEEPROM Write Access To Register Address Space Is Locked */
uint32_t :3; /*!< bit: 5.. 7 Reserved */
uint32_t SBLK:4; /*!< bit: 8..11 Blocks Number In a Sector */
uint32_t :4; /*!< bit: 12..15 Reserved */
uint32_t PSZ:3; /*!< bit: 16..18 SmartEEPROM Page Size */
uint32_t :13; /*!< bit: 19..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} NVMCTRL_SEESTAT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

/** \brief NVMCTRL APB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
Expand All @@ -746,7 +724,6 @@ typedef struct {
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */



#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief NVMCTRL register API structure */
typedef struct
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2 changes: 1 addition & 1 deletion mplabx/pic32cxsg/include/pic32cxsg41/component/sdhc.h
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Expand Up @@ -2164,7 +2164,7 @@ typedef union {
typedef union {
struct {
uint32_t HDATLL:4; /*!< bit: 0.. 3 High Line Level */
uint16_t :28; /*!< bit: 4..32 reserved */
uint32_t :28; /*!< bit: 4..32 reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SDHC_APSR_Type;
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35 changes: 14 additions & 21 deletions mplabx/pic32cxsg/include/pic32cxsg41/component/tcc.h
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Expand Up @@ -332,29 +332,22 @@ typedef union {
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */
uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */
uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */
uint32_t STATUS:1; /*!< bit: 3 Status Busy */
uint32_t COUNT:1; /*!< bit: 4 Count Busy */
uint32_t PATT:1; /*!< bit: 5 Pattern Busy */
uint32_t WAVE:1; /*!< bit: 6 Wave Busy */
uint32_t PER:1; /*!< bit: 7 Period Busy */
uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */
uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */
uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */
uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */
uint32_t CC4:1; /*!< bit: 12 Compare Channel 4 Busy */
uint32_t CC5:1; /*!< bit: 13 Compare Channel 5 Busy */
uint32_t :18; /*!< bit: 14..31 Reserved */
uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */
uint32_t :1; /*!< bit: 2 Reserved */
uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */
uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */
uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */
uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */
uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */
uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */
uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */
uint32_t BLANKPRESC:1; /*!< bit: 15 Fault A Blanking Prescaler */
uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */
uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t :8; /*!< bit: 0.. 7 Reserved */
uint32_t CC:6; /*!< bit: 8..13 Compare Channel x Busy */
uint32_t :18; /*!< bit: 14..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} TCC_SYNCBUSY_Type;
} TCC_FCTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define TCC_FCTRLA_RESETVALUE _UINT32_(0x00) /* (TCC_FCTRLA) Recoverable Fault A Configuration Reset Value */
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2 changes: 1 addition & 1 deletion mplabx/pic32cxsg/include/pic32cxsg41/component/usb.h
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Expand Up @@ -185,7 +185,7 @@ typedef union {
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_STATUS_BK_Type;
} USB_HOST_STATUS_BK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define USB_HOST_STATUS_BK_CRCERR_Pos _UINT8_(0) /* (USB_HOST_STATUS_BK) CRC Error Status Position */
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