How to understand the layout mapping in MMA Traits？

[MARD1NO]

Recently I'm learning Cute PPT, and I was confused about the layout mapping in MMA Traits:

How does it mapping logical value id to corrdinate?

For example, the LayoutA in SM80_8x8x4_F64F64F64F64_TN and SM80_16x8x8_F32F16F16F32_TN is same.

In SM80_8x8x4_F64F64F64F64_TN, the map we flatten is like:

tid:            0 1 2 3 ....
mapping: 0 8 16 24 1 9 17 25

thread1 will map to the position 8, and in 8x4 Colmajor layout, it will map to (0, 1), am I right?

but in second case SM80_16x8x8_F32F16F16F32_TN, I was confused about each thread need to take 4 fp16 value, how does it map?

[ccecka]

Looks like a slideware typo to me.

The following program

#include <cute/tensor.hpp>
using namespace cute;

int main()
{
  using MMA = MMA_Traits<SM80_16x8x8_F32F16F16F32_TN>;
  print("ALayout: "); print(typename MMA::ALayout{}); print("\n");
  print("BLayout: "); print(typename MMA::BLayout{}); print("\n");
  print("CLayout: "); print(typename MMA::CLayout{}); print("\n");
}

prints

ALayout: ((_4,_8),(_2,_2)):((_32,_1),(_16,_8))
BLayout: ((_4,_8),_2):((_16,_1),_8)
CLayout: ((_4,_8),(_2,_2)):((_32,_1),(_16,_8))

which makes a lot more sense: ALayout has size-4 in the V-mode and BLayout has size-2 in the V-mode.

Looks like you've got the right idea, but check out the MMA_Atom documentation as well:
https://github.com/NVIDIA/cutlass/blob/main/media/docs/cute/0t_mma_atom.md

[ccecka]

That's in the documentation:
https://github.com/NVIDIA/cutlass/blob/main/media/docs/cute/0t_mma_atom.md

[thakkarV]

I fixed this in my slides for SIAM PP24 :)

[wanghongyu2001]

Hi, can you send me the correct link to the slides?

[thakkarV]

Not yet. They will be available after the talk

[lee-bin]

@thakkarV Are the fixed slides available now?