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_posts/archived/2015-07-10-memory-barriers-in-dot-net.aspx.md

@@ -8,6 +8,10 @@ tags: [memory barrier, fence, intel, intel64, amd64, amd, reordering, processor]
 Nonblocking programming can provide performance benefits over locking, but getting it done right is significantly harder and requires careful testing. 
 When it comes to memory barriers, there is all sorts of confusion and misleading information. Because memory barrier can be counterintuitive, using them wrongly is easy, and applying them correctly requires a lot of effort and headache. The benefits memory barriers provide may not be worth it in most high-level applications. However, memory barriers are handy in performance critical software.
 
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 In the past, a system with a single processor executed concurrent threads using a trick called "timeslicing", where one thread is running and the others are sleeping. This means that all memory accesses done by one thread appeared in an exact order to all the other running threads. This is called a sequential consistency model. Nowadays, multiprocessor systems are very common and concurrent threads are truly running at the same time, so sequential consistency is not guaranteed because:
 
 1. The compiler or JIT might re-order the memory instructions for optimization.