Table of Contents

• Introduction

• Testboard Schematic

• Procedure

• For Observing PLL Locking

• For Settling Time

• For VCO linearity and gain

• PLL

• SoC Package

• IO and PG PAD cells

• Using Openlane for Synthesis and Floorplanning

Introduction

In this project we are planning to test a PLL IP. The PLL IP is developed using SKY130 PDK. For this, we first develop a testboard and the test flow. The PLL IP to be tested is included in the SOIC-24 package to communicate with external circuitry present in the testboard. The package consists of PAD cells from SKY130 IO and Periphery library. Similarly, Power on Reset circuit is used from Caravel repository to provide enable_h signal to PAD cells. Using LEF and Verilog files of PAD cells used, Power on Reset circuit and PLL IP to be tested and top level verilog module, we do synthesis and floorplanning. To complete the process, PNR is to be done.

Testboard schematic

Here, we are testing the PLL with reference clock generated from Pulse generator which is present outside the SoC.

Procedure:

Connect 1.8V, 3.3V, GND and 5V power supply for testing and also 0.2V to 1.2V varying power supply generator at specified positions in schematic.

For Observing PLL Locking

1. EN_VCO is made HIGH and EN_CP is made HIGH with switches S1 and S2. GND is applied at VCO_IN through switch S3.

2. Pass 10uA current through B_CP with switch S4 HIGH.

3. Connect indicated position CLK’ to Oscilloscope CH. II to observe the output.

4. Pulse generator will cause a sinusoidal wave(or square wave) to be applied to PLL inside SoC and observe the PLL input clock signal on oscilloscope CH.I which is available as REF_CLK (put oscilloscope in dual mode).

PLL is locked when the phase difference between the REF and CLK’ signals are constant.

Let, N = 5 for below figure,

For Settling Time

Similarly, settling time can be measured by observing the output in oscilloscope. Here, Tlock is the settling time for the observed frequency. After Tlock , the PLL is phase locked.

For VCO linearity and gain

1. EN_CP is made LOW and EN_VCO is made HIGH.

2. VCO control voltage is applied at VCO_IN.

3. A voltage V1 is forced onto the VCO_IN.

4. After settling, the corresponding output frequency F1 of the VCO is measured at pin5 from oscilloscope.

5. A higher voltage V2 is then forced onto the pin4.

6. After settling, the corresponding output frequency F2 of the VCO is measured.

After taking the above measurements the VCO gain can be determined using the following relationship.

In certain applications it may be necessary to determine VCO non-linearity, this can be determined by taking incremental measurements of the VCO gain between the points V1 and V2.

PLL

The PLL IP to be tested is considered as the one given in figure below:

SoC Package

The SoC package used for testing of PLL IP is SOIC-24 shown below:

IO and PG PAD cells

Here, we are using the SKY130 IO and Periphery PAD cells for developing the SoC package. The PAD cells used are shown below and also a table for their reason of use.

The PAD cells used are listed below:

Using Openlane for Synthesis and Floorplanning

For developing the SoC, we use opensource flow Openlane. Here, we have done till synthesis and floorplannnig through Openlane. To perform the above mentioned operation, we use verilog blackbox technique. Here, we consider the IO and Periphery cells used, PLL IP to be tested and the Power on Reset circuit as a black box. For this we use their .lef and verilog files containing only the input output port description. The top level verilog file whose module name is pll_soc can be found here. Here, we have included all verilog files present in src directory as `include "*.v/.blackbox.v".

We follow the below mentioned steps:

1. Create a folder with the module name of top level verilog file in design directory.

                  cd vsdflow/work/tools/openlane_working_dir/openlane/designs/
   
                  mkdir pll_soc
   

2. Again create a new folder src inside pll_soc

                  cd pll_soc
                  
                  mkdir src
   

3. Inside the src directory place .lef files of all the IO and Periphery PAD cells used, the PLL IP to be tested and the Power on Reset circuit used.

                 avsdpll_1v8.lef
   
                 simple_por.lef
   
                 sky130_fd_io__top_gpiov2.lef
   
                 sky130_fd_io__top_ground_hvc_wpad.lef
   
                 sky130_fd_io__top_ground_lvc_wpad.lef
   
                 sky130_fd_io__top_power_hvc_wpad.lef
   
                 sky130_fd_io__top_power_lvc_wpad.lef
   

4. Place the top level verilog file pll_soc.v in the src directory.

   Also, place the verilog files with extension .blackbox.v present in the SKY130 IO and Periphery PAD cells library. For PLL IP to be tested and the Power on Reset circuit used, the verilog files with only the input output port description is placed.

                pll_soc.v
   
                avsdpll_1v8.v
   
                simple_por.blackbox.v
   
                sky130_fd_io__top_gpiov2.blackbox.v
   
                sky130_fd_io__top_ground_hvc_wpad.blackbox.v
   
                sky130_fd_io__top_ground_lvc_wpad.blackbox.v
   
                sky130_fd_io__top_power_hvc_wpad.blackbox.v
   
                sky130_fd_io__top_power_lvc_wpad.blackbox.v
   

   Above mentioned files are present under pllsoc/openlane/verilog.

5. Now, we have to add a config.tcl file in pll_soc directory. So, go to the terminal and run the following:

                cd vsdflow/work/tools/openlane_working_dir/openlane/
   

   and execute:

                export PDK_ROOT=<absolute path to where skywater-pdk and open_pdks reside>
   
                docker run -it -v $(pwd):/openLANE_flow -v $PDK_ROOT:$PDK_ROOT -e PDK_ROOT=$PDK_ROOT -u $(id -u $USER):$(id -g $USER) openlane:rc2
   
                 ./flow.tcl -design pll_soc -init_design_config   
   

This will create config.tcl file with default settings. We then modify the file with required configuration variables that can be seen from here. The information about configuration variables can be found [here] (https://github.com/efabless/openlane/blob/master/configuration/README.md). We have basically pointed the location of verilog and lef files present in src directory in config.tcl.

6. Repeat the commands mentioned in step 5 till the bash window opens. In the bash window, the interactive flow is executed.

                             ./flow.tcl -design pll_soc -interactive
   

7. Run the below mentioned commands sequentially.

                              package require openlane 0.9                                           //Setting up flow
   
                              prep -design pll_soc -overwrite
                              
                              
                              set lefs 	 [glob $::env(DESIGN_DIR)/src/*.lef]                     //The LEF file for macro
   
                              add_lefs -src $lefs
                              
   
                              run_synthesis                                                          //Synthesis
   

The output file can be found here.

                              init_floorplan_or                                                      //Floorplanning

The output DEF file can be found here

Future Works

• To perform PNR

Acknowledgement

• Kunal Ghosh, Co-founder, VSD Corp. Pvt. Ltd

• Openlane team, Efabless corporation

• Tim Edwards, Senior Vice President of Analog and Design at efabless corporation

• Praharsha Mahurkar, Maharashtra Institute of Technology

• Philipp Gühring, Developer at Falcontrol

• Nickson Jose, VLSI Engineer