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Merge remote-tracking branch 'origin/GP-4794_ZmmLaneSizes'
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@ryanmkurtz
ryanmkurtz committed Jul 29, 2024
2 parents 1b91a4b + fb13a1c commit d7c7fc0
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Showing 3 changed files with 195 additions and 63 deletions.
34 changes: 19 additions & 15 deletions Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/model/lang/Register.java
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Original file line number Diff line number Diff line change
Expand Up @@ -4,9 +4,9 @@
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
*
* http://www.apache.org/licenses/LICENSE-2.0
*
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Expand Down Expand Up @@ -64,8 +64,8 @@ public class Register implements java.io.Serializable, Comparable<Register> {
private Register baseRegister;
private String group;

/** Set of valid lane sizes **/
private TreeSet<Integer> laneSizes;
/** Bit vector of valid lane sizes **/
private long laneSizes;

/**
* Constructs a new Register object.
Expand Down Expand Up @@ -101,6 +101,7 @@ public Register(String name, String description, Address address, int numBytes,
this.typeFlags = typeFlags;
this.bigEndian = bigEndian;
this.bitLength = bitLength;
this.laneSizes = 0;

int leastSigByte = leastSignificantBit / 8;
int mostSigByte = (leastSignificantBit + bitLength - 1) / 8;
Expand Down Expand Up @@ -509,10 +510,10 @@ public boolean isValidLaneSize(int laneSizeInBytes) {
if (!isVectorRegister()) {
return false;
}
if (laneSizes == null) {
if (laneSizeInBytes > 64 || laneSizeInBytes < 1) {
return false;
}
return laneSizes.contains(laneSizeInBytes);
return (((1L << (laneSizeInBytes - 1)) & laneSizes) != 0);
}

/**
Expand All @@ -522,13 +523,19 @@ public boolean isValidLaneSize(int laneSizeInBytes) {
* lane sizes have been set.
*/
public int[] getLaneSizes() {
if (laneSizes == null) {
if (laneSizes == 0) {
return null;
}
int[] sizes = new int[laneSizes.size()];
int[] sizes = new int[Long.bitCount(laneSizes)];
int index = 0;
for (int size : laneSizes) {
sizes[index++] = size;
int size = 1;
long tmp = laneSizes;
while (tmp != 0) {
if ((tmp & 1) != 0) {
sizes[index++] = size;
}
tmp >>= 1;
size += 1;
}
return sizes;
}
Expand All @@ -546,16 +553,13 @@ void addLaneSize(int laneSizeInBytes) {
throw new UnsupportedOperationException(
"Register " + getName() + " does not support lanes");
}
if (laneSizeInBytes <= 0 || laneSizeInBytes >= numBytes ||
if (laneSizeInBytes <= 0 || laneSizeInBytes >= numBytes || laneSizeInBytes > 64 ||
(numBytes % laneSizeInBytes) != 0) {
throw new IllegalArgumentException(
"Invalid lane size: " + laneSizeInBytes + " for register " + getName());
}
if (laneSizes == null) {
laneSizes = new TreeSet<>();
}
typeFlags |= TYPE_VECTOR;
laneSizes.add(laneSizeInBytes);
laneSizes |= (1L << (laneSizeInBytes - 1));
}

}
96 changes: 80 additions & 16 deletions Ghidra/Processors/x86/data/languages/x86-64.pspec
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Original file line number Diff line number Diff line change
Expand Up @@ -76,6 +76,38 @@
<register name="MM5" group="MMX"/>
<register name="MM6" group="MMX"/>
<register name="MM7" group="MMX"/>
<register name="ZMM0" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM1" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM2" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM3" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM4" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM5" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM6" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM7" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM8" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM9" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM10" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM11" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM12" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM13" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM14" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM15" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM16" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM17" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM18" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM19" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM20" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM21" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM22" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM23" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM24" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM25" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM26" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM27" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM28" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM29" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM30" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM31" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM0" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM1" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM2" group="AVX" vector_lane_sizes="1,2,4,8"/>
Expand All @@ -92,22 +124,54 @@
<register name="YMM13" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM14" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM15" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM0" vector_lane_sizes="1,2,4,8"/>
<register name="XMM1" vector_lane_sizes="1,2,4,8"/>
<register name="XMM2" vector_lane_sizes="1,2,4,8"/>
<register name="XMM3" vector_lane_sizes="1,2,4,8"/>
<register name="XMM4" vector_lane_sizes="1,2,4,8"/>
<register name="XMM5" vector_lane_sizes="1,2,4,8"/>
<register name="XMM6" vector_lane_sizes="1,2,4,8"/>
<register name="XMM7" vector_lane_sizes="1,2,4,8"/>
<register name="XMM8" vector_lane_sizes="1,2,4,8"/>
<register name="XMM9" vector_lane_sizes="1,2,4,8"/>
<register name="XMM10" vector_lane_sizes="1,2,4,8"/>
<register name="XMM11" vector_lane_sizes="1,2,4,8"/>
<register name="XMM12" vector_lane_sizes="1,2,4,8"/>
<register name="XMM13" vector_lane_sizes="1,2,4,8"/>
<register name="XMM14" vector_lane_sizes="1,2,4,8"/>
<register name="XMM15" vector_lane_sizes="1,2,4,8"/>
<register name="YMM16" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM17" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM18" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM19" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM20" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM21" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM22" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM23" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM24" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM25" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM26" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM27" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM28" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM29" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM30" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM31" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM0" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM1" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM2" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM3" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM4" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM5" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM6" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM7" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM8" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM9" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM10" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM11" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM12" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM13" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM14" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM15" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM16" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM17" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM18" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM19" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM20" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM21" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM22" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM23" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM24" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM25" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM26" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM27" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM28" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM29" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM30" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM31" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="CF" group="FLAGS"/>
<register name="F1" group="FLAGS"/>
<register name="PF" group="FLAGS"/>
Expand Down
128 changes: 96 additions & 32 deletions Ghidra/Processors/x86/data/languages/x86.pspec
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Original file line number Diff line number Diff line change
Expand Up @@ -60,38 +60,102 @@
<register name="MM5" group="MMX"/>
<register name="MM6" group="MMX"/>
<register name="MM7" group="MMX"/>
<register name="YMM0" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM1" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM2" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM3" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM4" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM5" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM6" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM7" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM8" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM9" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM10" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM11" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM12" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM13" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM14" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM15" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM0" vector_lane_sizes="1,2,4,8"/>
<register name="XMM1" vector_lane_sizes="1,2,4,8"/>
<register name="XMM2" vector_lane_sizes="1,2,4,8"/>
<register name="XMM3" vector_lane_sizes="1,2,4,8"/>
<register name="XMM4" vector_lane_sizes="1,2,4,8"/>
<register name="XMM5" vector_lane_sizes="1,2,4,8"/>
<register name="XMM6" vector_lane_sizes="1,2,4,8"/>
<register name="XMM7" vector_lane_sizes="1,2,4,8"/>
<register name="XMM8" vector_lane_sizes="1,2,4,8"/>
<register name="XMM9" vector_lane_sizes="1,2,4,8"/>
<register name="XMM10" vector_lane_sizes="1,2,4,8"/>
<register name="XMM11" vector_lane_sizes="1,2,4,8"/>
<register name="XMM12" vector_lane_sizes="1,2,4,8"/>
<register name="XMM13" vector_lane_sizes="1,2,4,8"/>
<register name="XMM14" vector_lane_sizes="1,2,4,8"/>
<register name="XMM15" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM0" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM1" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM2" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM3" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM4" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM5" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM6" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM7" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM8" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM9" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM10" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM11" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM12" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM13" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM14" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM15" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM16" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM17" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM18" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM19" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM20" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM21" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM22" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM23" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM24" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM25" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM26" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM27" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM28" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM29" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM30" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM31" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM0" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM1" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM2" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM3" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM4" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM5" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM6" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM7" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM8" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM9" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM10" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM11" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM12" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM13" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM14" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM15" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM16" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM17" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM18" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM19" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM20" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM21" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM22" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM23" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM24" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM25" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM26" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM27" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM28" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM29" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM30" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM31" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM0" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM1" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM2" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM3" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM4" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM5" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM6" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM7" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM8" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM9" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM10" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM11" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM12" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM13" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM14" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM15" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM16" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM17" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM18" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM19" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM20" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM21" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM22" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM23" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM24" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM25" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM26" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM27" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM28" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM29" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM30" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM31" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="CF" group="FLAGS"/>
<register name="F1" group="FLAGS"/>
<register name="PF" group="FLAGS"/>
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