Here there are all the material and labs made in the SKY130 PD Workshop.
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Day 1: Inception of open-source EDA, OpenLANE and SKY130 PDK
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Day 2: Good floorplan vs bad floorplan and introduction to library cells
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Day 3: Design library cell using Magic Layout and ngspice characterization
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Day 4: Pre-layout timing analysis and importance of good clock tree
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Day 5: Final steps for RTL2GDS using tritonRoute and openSTA
First we go to the folder where the openlane and pdks folders are located. For this case the adress was:
cd work/tools/openlane_working_dir/
If we get into the pdks folder, we will see three folders that have all the pdks necesary for the openlane flow.
Inside this folder there are all the pdks of skywater, all the timing, .lef, .tech, and information files.
Inside this folder there ares some scripts that make the skywater pdk compatible with the silicon foundries pdks.
Inside this folder there are to more folders: libs.tech and libs.ref. The first one contains files for the tools used in the openlane flow, like magic, netgen, kalayout, etc.
And in the second one there are the files with information about the technology.
Here is where we are going to run all the openlane flow.
Inside this folder there is the designs folder, where all the design are located. In this case we are going to work with picorv32a design.
Here there is the verilog file.
This file contains some information about the design like clock period and location of the design files.
This file has same information than the config.tcl, however this one is more relevant for the openlane flow.
For starting openlane we open a new terminal window and run docker. In the docker's bash, we start openlane interactively, and in the openlane's bash we prepare for runing the flow.
$ docker
bash-4.2$ ./flow.tcl -interactive
% package require openlane 0.9
Before synthesis it is necesary to get ready. Some folders and files must be created for the synthesis and th other steps of th flow.
prep -design picorv32a
When the preparation is ready a folder called "runs" will be created in the picorv32a folder. Inside this folder there are all the folders needed for storing all the reports and files generated by all the steps of th openlane flow.
Once we are ready, we run the synthesis. This will take no more than 5 minutes.
run_synthesis
When synthesis is completed there will appear some reports inside the runs folder that was already mention.
We go to the synthesis folder to see the generated reports.
For this lab we will see the statistics report, in order to know the number of flip-flop and get the flop rate.
From this report we can get the FR, and the total chip area of the module.
No of flip-flop = 1613
No of cells = 14876
FR = 0.10843
Chip area = 147712.9184
This step of the openlane flow places all the standard cells, logical gates, and pins on the silicon chip. Also make sure that each module is located in a good way, taking into acount their dimentions giving a minimum space for each module, the netlist to put them as nearest as possible to their conections minimizing the length of the path from the pin to the module or between modules, and always try to use the minimum chip area as posible.
In order to have a good floorplan is recomendable to follow this steps:
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Define width and heigh of the core and die: setting good dimentions for the core and die is important, becasuse more area its more expensive, however if we set small dimentions it won't be space for a good module placing. There are two measurements that should be also specify.
$$Utilization\ factor\ =\ \frac{Area\ ocupied\ by\ netlist}{Total\ area\ of\ the\ core}$$ $$Aspect\ ratio\ =\ \frac{Height}{Width}$$ -
Define locations of preplaced cells: The preplaced cells are cells that are instanced just once, and they can be use multiple times. Some preplaced cells are memory, clock gating, mux and comparator. These cells are placed manually by the user before the automated place of the cells, this automatic placing algorithm will use the remaining space for placing the other cells.
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Surround pre-placed cells with decopuling capcitor: The decopubling capacitors are between VDD and VSS and they are placed near to the preplaced cells because they are used to stabilize the supply voltage for the preplaced cells when there is a transition from 1 to 0 or 0 to 1. Whithout the decoupling capacitors when there is a transition the VDD voltage decreases because of the amount of require charge.
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Power planning: Here there are made a number of vertical and horizontal VDD and VSS routes for getting closer the suply voltages to each cells.
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Pin palcement: The pins should be placed in a good way in order to have the inputs and outputs pins of somo module near.
Inside the work/tools/openlane_working_dir/openlane/configuration folder there is a README file that contains all the variables with an explanation that can be used to edit the floorplan stage depending on what the designer wants to do.
In the same folder there is a .tcl file that contains the default values for the floorplan.
These parameters can be modified in work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/04-08_14-15/config.tcl file and the parameter will be overwrited However the more priority file is the config.tcl located in the project folder.
For running floorplan the next command must be executed in the openlane folder.
run_floorplan
When the floorplan is done, the results can be checked in the next folder in the .def file.
In the results we can observe the area of the die in microns.
To visualized the floorplan we can open magic:
And we will see this layout
This stage consist in three steps:
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Binding netlist with physical cells: Here it binds each module of the netlist with a physical cell that have a height and a width
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Placement: Here the physical binded cells are placed on the core in an optimal way in order to minimize the length of the connections between modules.
3.Optimize placement: Here th tool calculates the length of the requiered wires and capacitances associated to it, and for long wires buffers are added as repeaters to mantain the value of the signal.
For run placement the next command must be executed.
run_placement
To visualize the placement we can open magic.
We can zoom in to see the placed cells
The library cells contains all the information needed for each step of the flow like dimentions and timing information. These are needed to check the results of each step, for example in the floorplan the size of the core is decided depending on the number of cells and the dimentions of each one, for timing analisys it takes the timing inforation from the libraries and check setup and hold violations.
Inside these library cells there many standard cells with different characteristics, like sizes, threshhold voltages and gates. The designing standard cell flow is the next one:
- Inputs: The inputs that are needed are the pdks that conatin the rules and specifications stablish by the foundry.
- Design steps : Spice is used for simulated the circuit and also the layout is designed.
- Outputs: The outputs are the spice netlist with capacitances and resistances and the timing, noise and power libs.
For timing characterization some concepts must be defined.
| Timing threshhold definitions | Percentage |
|---|---|
| low rise th | 20% |
| high rise th | 80% |
| low fall th | 20% |
| high fall th | 80% |
| in rise th | 50% |
| out rise th | 50% |
| in fall th | 50% |
| out fall th | 50% |
The values that are used to characterize a cell are.
We are not going to design the inverter layout, so we get from the next git hub repository (https://github.com/nickson-jose/vsdstdcelldesign) by nickson-jose.
To copy this repo to our machine, we go to the openlane folder.
/home/niorcasitas07/Desktop/work/tools/openlane_working_dir/openlane
For cloning the repository.
git clone https://github.com/nickson-jose/vsdstdcelldesign
Then we copy the sky130A.tech file inside the folder of the repository, in order to have it in the same folder at the moment of opening magic.
We have all ready for see the inverter layout in magic. To open magic we execute the next command.
We can verify that this layout correspond to an inverter layout with the help of magic. Using the command "what" we can check that the upper transistor is a pmos and the lower one is a nmos. In adition all the conections are correctly done, both drains are conected to the output, both gates to the input, the pmos source is conected to VDD, and the nmos source is conected to VSS.
When we have the layout completed without any drc violations. We proceed to extrac an spice file from the layout, to simulate this cell with ngspice and characterize it.
For extrac the spice file we run the next commands in the magic console.
extract all
ext2spice cthresh 0 rthresh 0
ext2spice
This will create two files with the extensions .ext and .spice
Inside the spice document there is the netlist extracted from the layout with parasitics.
For running a simulation its necesary to add the simulation profile, the voltage sources as VDD and vin, and the libraries for the transistors. So we edit the .spice file.
For runing the simulation with ngspice we run the next command.
ngspice sky130_inv.spice
The simulation is completed but to see a graphic with the input and output wave we have to run the next command in the ngspice bash.
plot y vs time a
And we get the plot.
For getting the timing characterization, we use the graphic and the ngspcice bash to get the needed values.
| Timing values | Times |
|---|---|
| rise time | 63.71 ps |
| fall time | 42.56 ps |
| rise delay | 60.83 ps |
| fall delay | 27.58 ps |
To get our .lef file from our standard inverter cell layout, first we have to check some paramaters of the dimentions of the cell and the placing of the pins. This will depend on the minimum width (pitch) of the layers (metal 1, metal 2, etc..). We can see this parameters in the next directory:
Follow the next recomendation:
- The width of the standard cell must be an odd multiple of the vertical metal pitch.
- The heigh of the cell must be such that the VDD and VSS pins match with the power distribution donde in the floorplan
- The input and output pins must be in some interception of the grid.
Once we have completed all the requirements we can get the .lef file. For this we will write the next command in the magic console.
lef write
This will create a .lef file with the same name of the magic file, and in the same directory.
Inside the .lef file there are the pins and cell dimentions, that are use at the placement stage.
To have our cell inside the openlane flow we have to copy the .lef file into the src folder inside the picorv32a design.
cp sky130_vsdinv.lef /home/niorcasitas07/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/src
And we have also to cpoy the .lib files that are inside the cloned repository.
cp sky130_fd_sc_hd_* /home/niorcasitas07/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/src
To add the .lef file, we have to modify the config.tcl file inside picorv32a folder, adding the next variables.
set ::env(LIB_SYNTH) "$::env(OPENLANE_ROOT)/designs/picorv32a/scr/sly130_fd_sc_hd__typical.lib"
set ::env(LIB_FASTEST) "$::env(OPENLANE_ROOT)/designs/picorv32a/scr/sly130_fd_sc_hd__fast.lib"
set ::env(LIB_SLOWEST) "$::env(OPENLANE_ROOT)/designs/picorv32a/scr/sly130_fd_sc_hd__slow.lib"
set ::env(LIB_TYPICAL) "$::env(OPENLANE_ROOT)/designs/picorv32a/scr/sly130_fd_sc_hd__typical.lib"
set ::env(EXTRA_LEFS) [glob
$::env(OPENLANE_ROOT)/designs/$ ::env(DESIGN_NAME)/src/*.lef]
We run openlane as we have done before but with the next extra stpes.
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs
And then we run synthesis, floorplan and placement. This will generate a .lef and .def file. We can visualizae the layout with magic.
magic -T /home/niorcasitas07/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.placement.def &
If we zoom in we would see our cell implemented in the placement.
For the timing analysis we can use two different tools.
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OpenSTA : This tool allow us to edit the netlist and check the timing parameters: This tool works out of the openlane flow so you can try different strategies to solve our timing problems and when we have done it we have to overwrite the verilog file generated by the synthesis, for the verilog of the netlist generated by openSTA.
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Openroad : This tool works inside the openlane flow. So the changes you make using openroad will be applied to the netlist.
For using this tool we must have two extra file: a .conf inside the openlane directory and the ohter one a .sdc inside the picorv32a/src/ directory. For this case they were edited like the following files.
Then you go the openlane folder an run the next command.
sta sta.conf
For using this tool you run the next command inside the openlane bash.
openroad
Once we are using the openroad bash we run the next commands and at the end we will get a timing report. To exit of the tool we run the command exit.
read_lef /openLANE_flow/designs/picorv32a/runs/final/tmp/merged.lef
read_def /openLANE_flow/designs/picorv32a/runs/final/results/cts/picorv32a.cts.def
write_db pico_cts.db
read_db pico_cts.db
read_verilog /openLANE_flow/designs/picorv32a/runs/final/results/synthesis/picorv32a.synthesis_cts.v
read_liberty $::env(LIB_SYNTH_COMPLETE)
link_design picorv32a
read_sdc /openLANE_flow/designs/picorv32a/src/my_base.sdc
set_propagated_clock [all_clocks]
report_checks -path_delay min_max -format full_clock_expanded -digits 4
For our case the first time we run the synthesis we get the next timing results.
So as we can see we have a slack problem violation so we have to solve. To do it we can change some variables of the synthesis that improve the delay but the area is also increased. So its a trade off between those characteristics.
set ::env(SYNTH_STRATEGY) "DELAY 1"
set ::env(SYNTH_SIZING) 1
Running the synthesis after this changes we solve the timing problems.
Our slack is a positive value, and the slew's (tns and wns) are zero.
The clock tree synthesis is one of the most important steps of the openlane flow: Here the clock distribution paths are made very carefuly. The clock distribution net must be design very carefuly in order to get a minimum skew between the clock signal that arrives to each flip-flop. For this purpose the algorithm try to make the same legth for each clock path, and add buffer between stages to buff the clock signal, and to contribute mimimizing the skew.
This step must be run after synthesis, floorplan and placement steps.
run_cts
In this step all the power network is design and generated. This include the straps and rails where standard cells will be suplied, and also the power ring for the preplaced cells in order not to find any strap or rail on the preplaced cell.
For running this step we have to execute the command below.
run_gen_pdn
When the generation is completed, we can see the dimentions and layers for the straps and rails.
This is the last step of the flow . It is executed in two stages: the first one the fast root tool make a global rouitng ensuring all the connections are done and generates a route guide. The second one takes the route guide generated by the first stage, and start optimizing and solving all the DRC problems that can be generated, iterating many times until there are no DRC errors.
For running this step, execute the next comamnd.
run_routing
We can see that at lower number of iterations there are more DRC erros. And at the end there are no DRC erros.
Finally, the result of the routing stage generates a .spef file that contains the parasitics extracted from the routed layout.
