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[AArch64] Use implicitTrunc in isBitfieldDstMask() (NFC)
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This code intentionally discards the high bits, so set
implicitTrunc=true. This is currently NFC but will enable an
APInt assertion in the future.
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nikic committed Oct 21, 2024
1 parent af6e188 commit e2074c6
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Showing 2 changed files with 21 additions and 1 deletion.
4 changes: 3 additions & 1 deletion llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2792,7 +2792,9 @@ static bool isBitfieldDstMask(uint64_t DstMask, const APInt &BitsToBeInserted,
"i32 or i64 mask type expected!");
unsigned BitWidth = VT.getSizeInBits() - NumberOfIgnoredHighBits;

APInt SignificantDstMask = APInt(BitWidth, DstMask);
// Enable implicitTrunc as we're intentionally ignoring high bits.
APInt SignificantDstMask =
APInt(BitWidth, DstMask, /*isSigned=*/false, /*implicitTrunc=*/true);
APInt SignificantBitsToBeInserted = BitsToBeInserted.zextOrTrunc(BitWidth);

return (SignificantDstMask & SignificantBitsToBeInserted) == 0 &&
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18 changes: 18 additions & 0 deletions llvm/test/CodeGen/AArch64/bitfield-insert.ll
Original file line number Diff line number Diff line change
Expand Up @@ -735,3 +735,21 @@ define i32 @orr_not_bfxil_test2_i32(i32 %0) {
%4 = or i32 %2, %3
ret i32 %4
}

define i16 @implicit_trunc_of_imm(ptr %p, i16 %a, i16 %b) {
; CHECK-LABEL: implicit_trunc_of_imm:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: and w8, w1, #0xffffe000
; CHECK-NEXT: mov x9, x0
; CHECK-NEXT: mov w10, w8
; CHECK-NEXT: mov w0, w8
; CHECK-NEXT: bfxil w10, w2, #0, #1
; CHECK-NEXT: strh w10, [x9]
; CHECK-NEXT: ret
entry:
%and1 = and i16 %a, -8192
%and2 = and i16 %b, 1
%or = or i16 %and2, %and1
store i16 %or, ptr %p
ret i16 %and1
}

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